Browsing by Author "Chang, Ching-Yun"

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A Novel Sealing Redistribution Layer Approach for Through-Glass via Fabrication
(2017-03-01)
Lee, Shih-Wei
;
Chang, Geng-Ming
;
Chang, Ching-Yun
;
Chen, Kuan-Neng
;
電子工程學系及電子研究所
A sealing redistribution layer (RDL) approach for the interposer fabrication is developed to simplify the conventional bottom-up process flow. By using this approach, bottom-up plating can achieve the integration of Cu-filler plating and its bottom RDL simultaneously. In this paper, through-glass via in glass interposer or 3-D integration is fabricated using the proposed approach. The electrical measurement and reliability tests indicate that the proposed approach can be an attractive candidate for interposer fabrication with great performance.
Development and Electrical Investigation of Through Glass Via and Through Si Via in 3D Integration
(2017-01-01)
Chang, Geng-Ming
;
Lee, Shih-Wei
;
Chang, Ching-Yun
;
Chen, Kuan-Neng
;
電子工程學系及電子研究所
In this research, an optimized process scheme for through glass via (TGV)/through silicon via (TSV) fabrication is proposed to solve the difficulty of copper (Cu) filling in TGV/TSV. Kelvin structure, daisy chain, and comb structure are fabricated for evaluating electrical performance. Comparison between TGV and TSV shows that the power loss and overall process steps (cost) of TGV is lower than TSV for 3D interconnect. Moreover, daisy chain structure at chip-level is fabricated and investigated on its reliability including thermal cycling and humidity test. Finally, TGV/TSV without voids and V-shape pits formed at the filler are successfully fabricated and demonstrated at chip-level with 50-mu m TGV/TSV and 200-mu m thinned wafers.
Fine-Feature Cu/In Interconnect Bonding Using Single Sided Heating and Chip-to-Wafer Bonding Technology
(2017-03-01)
Lee, Shih-Wei
;
Chang, Ching-Yun
;
Chang, Geng-Ming
;
Chen, Kuan-Neng
;
電子工程學系及電子研究所
A submicron-thick Cu/In bonding by using single sided heating approach has been successfully demonstrated on chip-to-wafer-level without antioxidant metal coating. The single sided heating approach can successfully prevent oxidation of Cu metal on the wafer during bonding. As compared with double sided heating method, a lower specific contact resistance can be obtained in single sided heating method. In addition, post-bonding annealing can further improve the bonding quality. Excellent electrical performances of reliability tests show a great potential for future highly dense interconnect.
Single Sided Heating Method for Chip-to-Wafer Bonding with Submicron Cu/In Interconnects
(2016)
Chang, Ching-Yun
;
Lee, Shih-Wei
;
Chang, Geng-Ming
;
Chen, Kuan-Neng
;
電子工程學系及電子研究所
In this research, a single sided heating method is developed to solve the issue of metal oxidation at bottom substrate without antioxidant metal coating in chip-to-wafer bonding. By using optimized bonding parameter, the bonding quality and electrical performance is better than double sided heating in chip-to-wafer bonding. With the help of Cu/In low temperature bonding and single sided heating approach, chip-to-wafer bonding is successfully developed. With the additional annealing process, the bonding duration of single sided heating bonding can be reduced to keep the cost down. Interconnects also maintain good electrical properties after reliability test such as TCT and unbiased HAST. These results prove that the single sided heating method is able to provide good bonding quality and reliability for chip-to-wafer bonding process.