Browsing by Author "Chang, Edward Y."

Now showing 1 - 12 of 12

A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effects
(2014)
Hung, C. M.
;
Li, K. C.
;
Hsieh, E. R.
;
Wang, C. T.
;
Kou, C. I.
HEMT suffers from parasitic resistance (R-sd) and capacitance(C-gd) effects with the shrinking of channel length, leading to degraded performance in logic and RF applications. A new while simple method to extract parasitic RC has been proposed to construct accurate transport parameters in HEMTs. In comparison to the constant-R-sd method, this new voltage dependent method provides more convincing results, especially for very short channel devices. On the other hand, an accurate C-gd correction method has also been incorporated to adequately represent the mobility. Finally, a guideline to design high performance HEMTs has been proposed.
Evaluation of an InAs HEMT with source-connected field plate for high-speed and low-power logic applications
(2019-07-01)
Yao, Jing Neng
;
Lin, Yueh Chin
;
Lin, Min Song
;
Huang, Ting Jui
;
Hsu, Heng Tung
In this study, we have presented a source-connected field plate (SCFP) InAs high electron mobility transistor (HEMT) and evaluated its potential for using in high-speed and low-power logic applications. The fabricated device demonstrated good electrical characteristics including low subthreshold swing (SS) of 76 mV/decade, drain induced barrier lowering (DIBL) of 44 mV/V, I-ON/I-OFF ratio of 2.4x10(4), an off-state gate leakage current of less than 5x10(-6) A/mm and a G(m,max) of 1100 mS/mm at V-DS = 0.5 V. When increasing the drain-source bias (V-DS) to 1.0 V, the G(m,max) increased to 1750 mS/mm with a cut-off frequency of 113 GHz. These results revealed that the fabrication of source-connected field plate InAs HEMTs achieved excellent device performance for high-speed and low-power logic applications.
Gallium Nitride (GaN) High-Electron-Mobility Transistors with Thick Copper Metallization Featuring a Power Density of 8.2 W/mm for Ka-Band Applications
(2020-02-01)
Lin, Y. C.
;
Chen, S. H.
;
Lee, P. H.
;
Lai, K. H.
;
Huang, T. J.
Copper-metallized gallium nitride (GaN) high-electron-mobility transistors (HEMTs) using a Ti/Pt/Ti diffusion barrier layer are fabricated and characterized for Ka-band applications. With a thick copper metallization layer of 6.8 mu m adopted, the device exhibited a high output power density of 8.2 W/mm and a power-added efficiency (PAE) of 26% at 38 GHz. Such superior performance is mainly attributed to the substantial reduction of the source and drain resistance of the device. In addition to improvement in the Radio Frequency (RF) performance, the successful integration of the thick copper metallization in the device technology further reduces the manufacturing cost, making it extremely promising for future fifth-generation mobile communication system applications at millimeter-wave frequencies.
Growth of GaAs epitaixial layers on Si substrate by using a novel GeSi buffer layer
(2005-02-03)
Chang, Edward Y.
;
Luo, Guangli
;
Yang, Tsung Hsi
;
Chang, Chung Yen
This invention provides a process for growing Ge epitaixial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and subsequently growing a GaAs layer on Ge film of the surface of said Ge epitaixial layers by using metal organic chemical vapor deposition (MOCVD). The process comprises steps of, firstly, pre-cleaning a silicon wafer in a standard cleaning procedure, dipping it with HF solution and prebaking to remove its native oxide layer. Then, growing a high Ge-composition epitaixial layer, such as Si0.1Ge0.9 in a thickness of 0.8 μm on said Si substrate by using ultra-high vacuum chemical vapor deposition under certain conditions. Thus, many dislocations are generated and located near the interface and in the low of part of Si0.1Ge0.9 due to the large mismatch between this layer and Si substrate. Furthermore, a subsequent 0.8 μm Si0.05Ge0.95 layer, and/or optionally a further 0.8 μm Si0.02Ge0.98 layer, are grown. They form strained interfaces of said layers can bend and terminate the propagated upward dislocation very effectively. Therefore, a film of pure Ge is grown on the surface of said epitaixial layers. Finally, a GaAs epitaixial layer is grown on said Ge film by using MOCVD.
Growth of GaAs expitaxial layers on Si substrate by using a novel GeSi buffer layer
(2007-06-14)
Chang, Edward Y.
;
Luo, Guangli
;
Yang, Tsung-Hsi
;
Chang, Chun-Yen
This invention provides a process for growing Ge epitaixial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and subsequently growing a GaAs layer on Ge film of the surface of said Ge epitaixial layers by using metal organic chemical vapor deposition (MOCVD). The process comprises steps of, firstly, pre-cleaning a silicon wafer in a standard cleaning procedure, dipping it with HF solution and prebaking to remove its native oxide layer. Then, growing a high Ge-composition epitaixial layer, such as Si0.1Ge0.9 in a thickness of 0.8 μm on said Si substrate by using ultra-high vacuum chemical vapor deposition under certain conditions. Thus, many dislocations are generated and located near the interface and in the low of part of Si0.1Ge0.9 due to the large mismatch between this layer and Si substrate. Furthermore, a subsequent 0.8 μm Si0.05Ge0.95 layer, and/or optionally a further 0.8 μm Si0.02Ge0.98 layer, are grown. They form strained interfaces of said layers can bend and terminate the propagated upward dislocation very effectively. Therefore, a film of pure Ge is grown on the surface of said epitaixial layers. Finally, a GaAs epitaixial layer is grown on said Ge film by using MOCVD.
Improvement in RF performance of 40-nm InAs-channel based HEMTs using Pt gate sinking with two-step recess processes technology
(2010-12-01)
Kuo, Chien-I
;
Hsu, Heng-Tung
;
Wu, Chien-Ying
;
Chang, Edward Y.
;
Chen, Yu-Lin
Forty-nanometer lnAs HEMT devices fabricated by two-step recess and Pt-buried gate were demonstrated for low-noise and low-power millimeter wave applications. The device exhibited a high transconductance of 1650 mS/mm at a drain voltage of 0.5 V. Improvement of the current-gain cutoff frequency from 395 GHz to 423 GHz was achieved with minimum noise figure below 2.5 dB up to 64 GHz at only 4.33 mW DC power consumption level. Besides, the output conductance was decreased from 2400 mS/ mm to 325 mS/mm. These superior performances are attributed to mitigation of the short-channel effect through the proposed technology. (C) 2010 Elsevier B.V. All rights reserved.
Improvement on the noise performance of InAs-based HEMTs with gate sinking technology
(2010-11-01)
Hsu, Heng-Tung
;
Kuo, Chien-I
;
Chang, Edward Y.
;
Kuo, Fang-Yao
;
材料科學與工程學系
Improvement on the RF and noise performance for 80 nm InAs/In(0.7)Ga(0.3)As high-electron mobility transistor (HEMT) through gate sinking technology is presented. After gate sinking at 250 degrees C for 3 min, the device exhibited a high transconductance of 1900 mS/mm at a drain bias of 0.5 V with 1066 mA/mm drain-source saturation current. A current-gain cutoff frequency (f(T)) of 113 GHz and a maximum oscillation frequency (f(max)) of 110 GHz were achieved at extremely low drain bias of 0.1 V. The 0.08 x 40 mu m(2) device with gate sinking demonstrated 0.82 dB minimum noise figure and 14 dB associated gain at 17 GHz with only 1.14 mW DC power consumption. Significant improvement in RF and noise performance was mainly attributed to the reduction of gate-to-channel distance together with the parasitic source resistance through gate sinking technology. (C) 2010 Elsevier B.V. All rights reserved.
Mechanism of microstructure evolution for the Cu/Ta/GaAs structure after thermal annealing
(2007-04-01)
Chang, Chun-Wei
;
Lee, Huang-Ming
;
Chen, Chang-You
;
Chang, Li
;
Chang, Edward Y.
The diffusion behavior and microstructure evolution of Cu/Ta/GaAs multilayers after thermal annealing are investigated and the mechanism is proposed. A thin 30 nm tantalum layer was sputtered as a diffusion barrier to block Ga and As diffusion into the Cu layer. From the results of sheet resistance measurement, X-ray diffraction analysis, Auger electron spectroscopy and transmission electron microscopy, the Cu/Ta films on GaAs were found to be very stable up to 500 degrees C without Cu migration into GaAs. After annealing al 550 degrees C, the interfacial mixing of Ta with GaAs substrate occurred, resulting in the formation of TaAs2, and the diffusion of Ga through the Ta layer formed the Cu3Ga phase at the Cu/Ta interface. After annealing at 600 degrees C, the reaction of GaAs with Ta and Cu formed TaAs and Cu3Ga owing to Ga migration and interfacial instability.
Monolithic wideband linear power amplifier with 45% power bandwidth using pseudomorphic high-electron-mobility transistors for long-term evolution application
(2014-11-01)
Chiang, Che-Yang
;
Hsu, Heng-Tung
;
Chang, Edward Y.
;
材料科學與工程學系
;
Department of Materials Science and Engineering
A fully integrated, monolithic, wideband linear power amplifier using pseudomorphic high-electron-mobility transistor (pHEMT) technology has been developed for long-term evolution (LTE) applications. Implemented through the stacked field-effect transistor (stacked-FET) configuration, the amplifier exhibited a small signal gain of 15 dB and an output power of 25 dBm at 1 dB compression (P-idB) with a power-added efficiency (PAE) of 36% from 1.7 to 2.7 GHz yielding 45% power bandwidth. Moreover, when tested under a 10 MHz LTE-modulated signal, the amplifier achieved a 3% error-vector-magnitude (EVM) at 23 dBm output power over the entire power bandwidth. (C) 2014 The Japan Society of Applied Physics
Study of Enhancement-Mode Tri-Gate InAs HEMTs for Low Noise Application
(2019-01-01)
Wang, C.
;
Lin, Y. C.
;
Kuo, C. N.
;
Lee, M. W.
;
Yao, J. N.
An enhancement-mode tri-gate InAs HEMT is investigated for low noise application in this paper. The 3-D tri-gate structure is sidewall-gate-metal connected to InAlAs layers, the gate connection to the InAlAs layers increases their potential to the positive direction with increasing the gate bias, resulting gate control ability enhancement. Compared with planar device, the tri-gate device shows high transconductance and low noise figure. The enhancement-mode tri-gate device exhibits excellent low noise figure with less than 3.5 dB when the device operation frequency range of 18 GHz to 50 GHz.
Study of Thick Copper Metallization with WNx as Diffusion Barrier for AlGaN/GaN HEMTs
(2019-01-01)
Lin, Y. C.
;
Lee, M. W.
;
Tsai, M. Y.
;
Wang, C.
;
Yao, J. N.
In this study, the thick copper metallization with WNx as diffusion barrier is investigated for AlGaN/GaN HEMTs. The device current density, transconductance, ft, fmax, noise figure were evaluated for the device with and without thick copper interconnect metal, and the thermal stability test was performed after the device with copper metallization.
Use of Spin-On-Hard Mask Materials for nano scale patterning technology
(2008)
Wu, Wen-Hao
;
Chang, Edward Y.
;
Cheon, Hwan-Sung
;
Kim, Sang Kyun
;
Cho, Hyeon Mo
Amorphous Carbon Layer (ACL) and SiON system has been proven to be a good hardmask combination. These layers are formed by a high cost, low throughput CVD process. This paper discloses a reliable, low cost, high throughput process using a simple spin on layer structure. Through manipulation of various parameters, additional BARC layer is eliminated and the process is further simplified to a tri-layer structure. Also, PR/SiON/C-SOH (Carbon-Spin-On-Hardmask) system has been compared to PR / Si-SOH (Si-Spin-On-Hardmask) / C-SOH system and found their performances are comparable. This indicates the PR / Si-SOH / C-SOH process is an economical yet comparable substitute.