Browsing by Author "Chang, Fu-Ke"
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Item type:Item, A Universal VLSI Architecture for ReedSolomon Error-and-Erasure Decoders(2009-09-01) ;Chang, Hsie-Chia ;Lin, Chien-Ching ;Chang, Fu-Ke ;Lee, Chen-Yi電子工程學系及電子研究所This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syndrome calculator and Chien search block, as well as an on-the-fly inversion table for calculating error or errata values. After implemented with 0.18-mu m 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm silicon area, and the average core power consumption is 68.1 mW.Item type:Item, Universal architectures for Reed-Solomon error-and-erasure decoder(2005) ;Chang, Fu-Ke ;Lin, Chien-Ching ;Chang, Hsie-Chia ;Lee, Chen-Yi電子工程學系及電子研究所This paper presents the universal architecture for Reed Solomon (RS) error-and-erasure decoder that can accommodate any codeword with different code parameters and finite field definitions. In comparison with other reconfigurable RS decoders, the proposed design, based on the Montgomery multiplication algorithm, can support various finite field degrees, different primitive polynomials, and erasure decoding functions. In addition, the decoder features an on-the-fly finite field inversion table for high speed error evaluation. The area efficient design approach is also presented Implemented with 1.2V 0.13 mu m 1P8M technology, this decoder, correcting up to 16 errors, can operate at 300MHz and reach a 2.4Gb/s data rate. The total gate count is about 54K and the core size is 0.36mm(2). The average power consumption is 20.2m W.