Browsing by Author "Chang, HC"

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A (204,188) Reed-Solomon decoder using decomposed Euclidean algorithm
(2000)
Chang, HC
;
Cheng, CY
;
Tsai, SH
;
Lee, CY
;
電子工程學系及電子研究所
A (204, 188) Reed-Solomon decoder for DVB application is presented. The RS decoder features an area-efficient Key Equation Solver using a novel decomposed Euclidean algorithm. We implement the RS decoder using 0.35 mum CMOS 1P4M standard cells, where the total gate count is about 16K similar to 17K. Test results show that the RS decoder chip can run up to 87MHz.
A (208,192;8) Reed-Solomon decoder for DVD application
(1998)
Chang, HC
;
Shung, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The Digital Versatile Disk (DVD) is an emerging standard to meet the ever increasing storage capacity requirement of future high quality video and audio applications. In this paper, we implement a (208, 192; 8) Reed-Solomon decoder for the DVD Reed-Solomon product code (RS-PC). We propose a new area-efficient architecture which uses only three finite field multipliers (FFMs) to implement the inversion-less Berlekamp-Massey algorithm. The error value evaluator employs an algorithm-based GF(2(m)) inverter instead of an inversion ROM-table. We implement the (208, 192; 8) Reed-Solomon decoder using a 0.6 mu m SPDM CMOS technology with an area of 12.35 mm(2) (core area 6.45 mm(2)). The chip can run at 16.67MHz, while the DVD requirement is 3.74MHz. A minor error was found in this first version which a corrected in the second version of the chip.
A 3.33Gb/s (1200,720) low-density parity check code decoder
(2005)
Lin, CC
;
Lin, KL
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a new data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm(2) 0.18 mu m silicon area. The other 0.13 mu m chip with the 10.24mm(2) core can further reach a 5.92Gb/s data rate under 1.02V supply.
A dual mode channel decoder for 3GPP2 mobile wireless communications
(2004)
Lin, CC
;
Shih, YH
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
This paper presents a turbo and Viterbi decoder single chip for 3GPP2 standard. The turbo decoding with a maximum block length of 20,730 and Viterbi decoding with various coding rates are implemented to provide maximum 4.52Mb/s and 5.26Mb/s data rates respectively The memory access is reduced by the input caching scheme. And the system complexion is lowered by the efficient interleaver design. This chip is fabricated in a 0.18mum six-metal standard CMOS process, and the measured power dissipation is 83mW while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block.
A dynamic normalization technique for decoding LDPC codes
(2005)
Liao, YC
;
Lin, CC
;
Liu, CW
;
Chang, HC
;
電子工程學系及電子研究所
In this paper, a dynamic normalization technique is proposed to approximate the nonlinear operation in decoding LDPC codes. The criterion in determining the normalization factor is also presented with theoretical analysis. The proposed method improves the approximation accuracy as well as the error performance of min-sum algorithm. Furthermore, the hardware implementation benefits from a simplified normalization scheme, leading to reductions in complexity and implementation loss.
A low power turbo/Viterbi decoder for 3GPP2 applications
(2006-04-01)
Lin, CC
;
Shih, YH
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in wearable devices. This research investigates an optimized memory scheme and rescheduled data flow to reduce power consumption and chip area. The memory access is reduced by buffering the input symbols, and the area is reduced by reducing the embedded interleaver memory. A test chip is fabricated in a 1.8 V 0.18-mu m standard CMOS technology and verified to provide 4.25-Mb/s turbo decoding and 5.26-Mb/s Viterbi decoding. The measured power dissipation is 83 mW, while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block. The power consumption in Viterbi decoding is 25.1 mW in the 1-Mb/s data rate. The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s.
A low-power design for Reed-Solomon decoders
(2003-04-01)
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a low-power design for the Reed-Solomon (RS) decoder is presented. Our approach includes a novel two-stage syndrome calculator that reduces the syndrome computations by one-half, a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The test chip for (255,239) and (208,192) RS decoders are implemented by 0.25 mum CMOS 1P5M and 0.35 mum CMOS SPQM standard cells, respectively. Simulation results show our approach can work successfully and achieved large reduction of power consumption on the average.
A low-power Reed-Solomon decoder for STM-16 optical communications
(2002)
Chang, HC
;
Lin, CC
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a low-power Reed-Solomon (RS) decoder for STM-16 optical communications is presented. It mainly contains one (255,239) RS decoder and four 2K-bit embedded memory for correcting the received codewords. Except the novel syndrome calculator reducing half the syndrome computations, our proposal also features a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The (255,239) RS decoder is implemented by 0.25mum CMOS 1P5M standard cells with gate counts of 32.9K and area of 2.03 mm(2). Simulation results show our approach can work successfully at the data rate of 2.5-Gbps and achieve 80% reduction of power dissipation on the average.
A metamorphic high electron-mobitity transistor with reflowed submicron T-Gate for high-speed optoelectronics applications
(2003)
Lien, YC
;
Chang, EY
;
Chu, LX
;
Chang, HC
;
Lee, CS
A metamorphic high electron-mobility transistor (HEMT) manufactured with reflowed submicron T-gate using E-beam lithography for high-speed optoelectronics applications is developed. The In0.53Al0.47As/InGaAs HEMT uses InxAl1-xAs as the buffer layer between GaAs substrate and the InP lattice-matched HEMT structure. The T-gate developed has a gate length of 0.1 mum. The fabricated metamorphic HEMT has a saturation drain current of 280mA/mrn and a transconductance of 840mS/mm at V-DS=1.2V Noise figure for 160 mum gate-width device is less than 1 dB and the associated gain is up to 14dB at 18GHz. The device demonstrates a cut-off frequency f(T) of 150GHz and a maximum frequency f(MAX) up to 350GHz. The metamorphic HEMT developed has the potential for high-speed optoelectronics applications.
A new channel equalizer for OFDM-based wireless communications
(2005)
Chang, YM
;
Kuang, CW
;
Lin, CC
;
Sang, TS
;
Chang, HC
This paper presents a new channel equalizer for OFDM-based communication systems. The channel equalizer consists of the adaptive estimation of channel frequency response (CFR) and the signal recovery. CFR is obtained by the two-dimensional linear interpolation of pilots from the frequency axis and the time axis. To avoid the noise enhancement in signal recovery, maximum-likelihood sequence estimation (MLSE) is applied to improve 1.5dB in SNR while using Rayleigh fading channel model with 30Hz Doppler frequency shift. As compared to the linear equalizer without feedback, the division free approach provides more accurate signal recovery in circuit implementation.
A novel I-line phase shift mask (PSM) technique for submicron T-Gate formation
(2001)
Fu, DK
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Chang, HC
;
Fang, CY
;
Lee, CS
;
Chang, EY
Submicron T-gate formation using I-line stepper with phase shift mask (PSM) technique [1,2,3] has become very attractive for GaAs MMIC technology due to its low capital investment and high throughput. In this paper a novel submicron (<0.2mum) T-gate technology using phase shift mask technique is reported. The 8% half-tone PSM was selected for the definition of the isolated narrow space. Before lithography, 2500Angstrom SiN film was deposited on the wafer. After I-line PSM exposure and RIE etch of the silicon nitride film, openings with less than 0.25mum wide were formed on the SiN film. To further reduce the dimension of the openings, the wafer was then deposited addition 500Angstrom nitride and etched back using RIE without any mask. Less than 0.2mum openings were formed on the wafer after the dry etch. The wafer was then coated with another layer of photoresist to form lift-off structure. Gate length of 0.185mum was obtained using this technique. This novel process is a high throughput T-gate process compared to conventional E-beam lithography technology for GaAs MMIC production.
A power and area efficient multi-mode FEC processor
(2004)
Tseng, YC
;
Lin, CC
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
Forward Error Correction (FEC) is a key component in communication system which mostly contains scrambler, Reed-Solomon coding, interleaving, and trellis coding. For the performance and complexity issues, design parameters are different in various applications. In this paper, a multi-mode FEC processor is presented to meet different system requirements with a power and area efficient architecture. The proposed processor is fully compliant to ITU-T J.83 cable modem system including the reconfigurable Reed-Solomon decoder and memory-based universal convolutional interleaver. With 0.18um 1P6M CMOS technology, the simulation result shows the FEC decoder can work over 100MHz while costs 54.5K gate counts and two 376x8 bits embedded duel-port SRAM. The average power consumption in most critical mode is about 34.2mW at 100MHz. While running at 7MHz that meets symbol rate of cable modem, the power dissipation is 2.32mW.
A Reed-Solomon Product-Code (RS-PC) decoder chip for DVD applications
(2001-02-01)
Chang, HC
;
Shung, CB
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a Reed-Solomon Product-Code (RS PC) decoder for DVD applications is presented. It mainly contains two frame-buffer controllers, a (182, 172) row RS decoder, and a (208, 192) column RS decoder, The RS decoder features an area-efficient key equation solver using a novel modified decomposed inversionless Berlekamp-Massey algorithm. The proposed RS-PC decoder solution was implemented using 0.6-mum CMOS single-poly double-metal (SPDM) standard cells. The chip size is 4.22 x 3.64 mm(2) with a core area of 2.90 x 2.88 mm(2),where the total gate count is about 26K, Test results show that the proposed RS-PC decoder chip can support 4x DVD speed with off-chip frame buffers or 8x DVD speed with embedded frame buffers operating at 3 V.
An AS-DSP for forward error correction applications
(2005)
Hsiao, TY
;
Lin, CC
;
Chang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An application specific digital signal processor for channel coding is presented. The vector operations can improve both the performance of memory accesses and program code density. The special function units and datapaths for channel decoding accelerate the decoding speed and facilitate algorithm implementation. The processor had been fabricated in a 0.18 mu m CMOS 1P6M technology. The 2 chip size is 7.73 mm(2) including 18k bits embedded memory, and the power consumption is 141 mW while decoding Reed-Solomon code and convolutional code. In contrast with general purpose processor designs, the results show this chip has at least 50% improvement in code density and 66% data rate enhancement.
An etch back technique to achieve sub-micron T-gate for GaAsFETs using I-line stepper and phase shift mask (PSM)
(2002)
Fu, DK
;
Chen, SH
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Chang, HC
;
Chang, EY
;
材料科學與工程學系
In this study, an etch back process with I-line Stepper lithography and phase shift mask (PSM) is demonstrated for sub-micron T-gate fabrication. The opening after I-line lithography using PSM and first RIE etch of silicon nitride is 0.25mum. The opening after second silicon nitride deposition and RIE etch is decreased to 0.16mum. After metal deposition and lift-off, the developed T-shaped gate shows a footprint smaller than 0.2mum. The novel technique is a high throughput T-gate process compared to conventional E-beam technology and can be applied to mass production of high frequency GaAs-based FETs and MMIC.
Connect6
(2005-12-01)
Wu, IC
;
Huang, DY
;
Chang, HC
;
資訊工程學系
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Department of Computer Science
This note introduces the game Connect6, a member of the family of the k-in-a-row games, and investigates some related issues. We analyze the fairness of Connect6 and show that Connect6 is potentially fair. Then we describe other characteristics of Connect6, e.g., the high game-tree and state-space complexities. Thereafter we present some threat-based winning strategies for Connect6 players or programs. Finally, the note describes the current developments of Connect6 and lists five new challenges.
Design of a power-reduction viterbi decoder for WLAN applications
(2005-06-01)
Lin, CC
;
Shih, YH
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
In this paper, a 64-state four-bit soft-decision Viterbi decoder with power saving mechanism for high speed wireless local area network applications is presented. Based on path merging and prediction techniques, a survivor memory unit with hierarchical memory design is proposed to reduce memory access operations. It is found that more than 70% memory access can be reduced by taking advantage of locality. Moreover, a low complexity compare-select-add unit is also presented, leading to save 15% area and 14.3% power dissipation as compared to conventional add-compare-select design. A test chip has been designed and implemented in 0.18-mu m standard CMOS process. The test results show that 30 similar to 40% power dissipation can be reduced, and the power efficiency reaches 0.75 mW per Mb/s at 6 Mb/s and 1.26 mW per Mb/s at 54 Mb/s as specified in IEEE 802.11a.
Effect of the orientation of CdSe nanorods on the electron mobility of CdSe/P4VP nanodomains self-assembled within a poly(styrene-b-(4)-vinyipyridine) diblock copolymer thin film
(2006-03-01)
Li, CP
;
Yeh, SW
;
Chang, HC
;
Huang, JY
;
Wei, KH
Highly selective GaAs/Al0.2Ga0.8As wet etch process for the gate recess of low-voltage-power pseudomorphic high-electron-mobility transistor
(2000-08-01)
Chang, HC
;
Chang, EY
;
Chung, CC
;
Kuo, CT
;
材料科學與工程學系
A selective wet etch process for the gate recess of the GaAs power pseudomorphic high-electron-mobility transistors (pHEMT's) was developed. The power pHEMT's used in this study were epitaxially grown power Al0.2Ga0.8As/In0.2Ga0.8As pHEMT's with a 250 Angstrom GaAs cap layer and a 300 Angstrom Al0.2Ga0.8As electron-donating layer. The electron-donating layer was used as the etch-stop layer for the gate recess. A selectivity of 3400 : 1 was achieved for GaAs/Al0.2Ga0.8As layers using citric acid/tripotassium citrate/hydrogen peroxide etching solutions in this study. This is the highest selectivity for GaAs/AlxGa1-xAs selective etching reported so far. The pHEMT's processed using this selective etching demonstrated good device power performance, and the wet recess process did not cause any contamination or damage to the device. The test data indicates that this selective etch process can be of practical use for forming the gate recess of the power pHEMT's with good device performance and excellent electrical uniformity.
Low-noise metamorphic HEMTs with reflowed 0.1 mu m T-gate
(2004-06-01)
Lien, YC
;
Chang, EY
;
Chang, HC
;
Chu, LH
;
Huang, GW
A 0.1-mum T-gate fabricated using e-beam lithography and thermally reflow process was developed and applied to the manufacture of the low-noise metamorphic high electron-mobility transistors (MHEMTs). The T-gate developed using the thermally reflowed e-beam resist technique had a gate length of 0.1 mum and compatible with the MHEMT fabrication process. The MHEMT manufactured demonstrates a cutoff frequency f(T) of 154 GHz and a maximum frequency f(max). of 300 GHz. The noise figure for the 160 mum gate-width device is less than 1 dB and the associated gain is up to 14 dB at 18 GHz. This is the first report of a 0.1 mum MHEMT device manufactured using the reflowed e-beam resist process for T-gate formation.