Browsing by Author "Chang, Hsiang-Hung"

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3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)
(2018-01-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Chen, Shang-Chun
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Chang, Hsiang-Hung
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Chang, Tao-Chih
This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-mu m-diameter/ 50-mu m-length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12-mu m diameter are bonded using three step temperature bonding profile. Further stacked DRAM/ Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.
A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices
(2014-06-01)
Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Chang, Hsiang-Hung
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Lyu, Dian-Rong
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Hsu, Chao-Kai
A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon (similar to 3.6 mu m) and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme.
An RDL-First Fan-out Wafer-level Package for Heterogeneous Integration Applications
(2018-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
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Shen, Wen-Wei
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Huang, Shin-Yi
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Kuo, Tzu-Ying
Fan-out wafer-level packaging (FOWLP), a new heterogeneous integration technology, is gradually becoming an attractive solution. Compared with conventional 2.5D/3D IC structures, fan-out WLP does not use a costly interposer element and can have a thin, high-density, and low-cost IC packaging. In this study, a novel fan-out WLP with RDL-first method is demonstrated. Finite element method was used to optimize the warpage control of a reconstituted wafer and to identify the material properties and fabrication for the FOWLP. Calculation results were applied in the design of the test vehicle. Reliability testing of each component level was performed with different techniques such as temperature cycling test (TCT), high temperature storage (HTS) and thermal humidity storage test (THST). The demonstration of RDL-first WLP technology without interposer proves that it has excellent potential for heterogeneous integration applications.
Process Development and Material Characteristics of TSV-less Interconnection Technology for FOWLP
(2017-01-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Chang, Hsiang-Hung
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Kuo, Tzu-Ying
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Fu, Huan-Chun
Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface of RDL and carrier wafer is used for the separation of the reconfigured wafer and carrier wafer with laser de-bonding technology. Since release layer material is the key factor for de-bonding, these materials are evaluated to determine the quality. Test chips are flip-chip bonded onto a carrier wafer with 2 layers of RDL and passivation, following by wafer molding process. Wafers reveal a warp surface due to chemical material shrinkage and CTE mismatch during post mold curing. Warpage of molded wafer is needed to be optimized for equipment handling and the warpage characterization is collected to analyze by different processes. To examine the quality of the structure, electrical measurement is carried out and their respective results are presented.
Ultrathin Glass Wafer Lamination and Laser Debonding to Enable Glass Interposer Fabrication
(2015)
Shen, Wen-Wei
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Chang, Hsiang-Hung
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Wang, Jen-Chun
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Ko, Cheng-Ta
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Tsai, Leon
Interposer fabrication processes are applied in three-dimensional (3-D) integrated circuit (IC) integration to shorten the interconnection among different stacked chips and substrates. Because Si is a common material in semiconductor technology, Si interposers have been widely studied in many research activities. Compared with a Si wafer, glass substrates have the advantages of high resistivity, low dielectric constant, low insertion loss, adjustable coefficient of thermal expansion (CTE), and the possibility to use panel-size substrates as well as thin glass substrates (100 mu m) to avoid the costly thinning process for realization of low-cost 2.5-D ICs. Thus, glass interposer fabrication is studied thoroughly in this paper. Thin glass wafers have reduced mechanical stiffness. Therefore, handling and shipping thin glass wafers (<= 100 mu m) throughout the semiconductor fabrication and packaging assembly processes are critical. Temporary wafer bonding technology is used in this study to bond a thin glass wafer to a carrier to improve the rigidity. Vacuum lamination technology is used in this study as a bonding process to enhance the cost-effectiveness. After processing, the carrier is removed by laser debonding. The thin glass wafer with structures on both sides does not need to undergo a glass thinning process and saves a lot of cost compared to the traditional glass or Si interposer processes. Thin 300-mm glass wafers 100 mu m thick are evaluated as: (a) blank thin glass wafers and (b) thin glass wafers with through-glass vias (TGVs) 30 mu m in diameter. A UV laser with a wavelength of 308 nm, which has the benefit of less impact to the device, was adopted to laser debonding. This method also has several benefits such as high throughput, low temperature, zero-force debonding, and possible selective laser debonding. Adhesive and release layers are key enabling materials for thin glass handling. In addition, the use of a laminator for temporary bonding and laser debonding are included in this study. Based on the excellent fabrication, the thin glass interposer has great potential to be applied in 2.5-D integration applications.
Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology
(2018-08-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Wu, Sheng-Tsai
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Lee, Chia-Hsin
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Huang, Shin-Yi
In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.