Browsing by Author "Chang, Hsiu-Fu"

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Comparison of Electrical Characteristics of N-type Silicon Junctionless Transistors with and without Film Profile Engineering by TCAD Simulation
(2015)
Tsai, Jung-Ruey
;
Lin, Horng-Chih
;
Chang, Hsiu-Fu
;
Shie, Bo-Shiuan
;
Wen, Ting-Ting
Field-effect transistors (FETs) with junctionless (JL) channels have recently attracted much attention for various applications, such as metal-oxide semiconductor thin-film transistors (TFTs) [1], memory devices [2] and Si nanowire TFTs [3, 4]. The Si junctionless (JL) transistors employing high dopant concentration (>= 10(19) cm(-3)) in the source, drain, and nano-scaled channel have been demonstrated to provide excellent electrical characteristics. More recently, film profile engineering (FPE) concept for fabricating downscaled ZnO and IGZO TFTs [5, 6] have been proposed to obtain high-on/off current ratio and great subthreshold swing. Nevertheless, it emphasizes a significant issue of source/drain (S/D) series resistance on the downscaled device performance that needs to be further verified. In this work, electrical performance of downscaled N-type Si JL TFTs with FPE channel and conventional ones will be compared with each other by Sentaurus technology computer aided design (TCAD) simulation [7].
Reliability Analysis of Amorphous Silicon Thin-Film Transistors during Accelerated ESD Stress
(2015)
Tsai, Jung-Ruey
;
Wen, Ting-Ting
;
Yang, Shao-Ming
;
Sheu, Gene
;
Chang, Ruey-Dar
This work investigates the degradation of electrical characteristics of amorphous silicon thin-film transistors during the accelerated ESD stress with a 40V high voltage and a high/low current of 2 mA/0.1 mu A conditions. Both the leakage current and the threshold voltage shift are severe as the accelerated ESD stress applied at the gate region. The 40V accelerated ESD stress with a high current has more severe impact on the electrical performance of device than that with a low current.