Browsing by Author "Chang, J-H."

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Analytical Model to Evaluate the Role of Deep Trap State in the Reliability of NAND Flash Memory and its Process Dependence
(2016)
Yang, B-J.
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Wu, Y-T.
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Chiu, Y-Y.
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Shirota, R.
;
Kuo, T-M.
An elementary step of trap and detrap processes of electron in the tunnel oxide during program/erase in NAND Flash memory is precisely studied. Owing to the high electric field during program and erase (P/E), the electron trapping and detrapping occur at the same time. Consequently, the detrapping process only leaves electrons in the deeper trap energy state (Etrap) than 3.5 eV. In addition, as-grown trap density (Ne) and capture cross section (a) in the deep trap state can be specified to explain the measured data including the tunneling current modulation with cycling and the VT shift by oxide trap. The P/E endurance characteristics using dry and plasma oxidation processes are analyzed and compared. In both processes, a has the same value (4x10-17 cm(2)). However, Ne depends on the oxidation process. In dry oxidation, Ne is 1.88x10(19) cm(-3). On the other hand, in plasma oxidation, 30% reduction (1.25x10(19) cm(-3)) can be found.
Improvement of Oxide Reliability in NAND Flash Memories Using Tight Endurance Cycling with Shorter Idling Period
(2015)
Shirota, R.
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Yang, B-J.
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Chiu, Y-Y.
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Wu, Y-T.
;
Wang, P-Y.
It has been newly found that shorter intervals between program and erase operations can suppress the oxide degradation more significantly in a 0.05 to 5 sec timeframe. Our new analysis clearly demonstrates the following degradation phenomena: a longer interval yields more trapped charges near the Si surface and surface states. Our results also indicate that the oxide degradation occurs more significantly during the erase-to-program interval than in the program-to-erase interval. These findings suggest that the erasing step causes a self-induced positive FG potential yields an accumulation of trapped holes near the Si surface and also generates surface states during the interval from erase-to-program. In addition, regarding retention characteristics, larger Vt shifts caused by the reduction of surface states and electron detrapping of oxide charges are observed in the longer interval. Based on these results, a new NAND operation scheme is proposed to improve reliability in shorter intervals.
New Accurate Method to Analyze both Floating Gate Charge and Tunnel Oxide Trapped Charge Profile in NAND Flash Memory
(2014-01-01)
Shirota, R.
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Yang, B-J.
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Chiu, Y-Y
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Chen, H-T.
;
Ng, S-F.
New method to extract the amount of floating (FG) charge (Q(FG)) apart from oxide trapped charge (Q(OX)) generated by program and erase (P/E) cycles is proposed, for the first time. Q(FG) shift by P/E cycling shows asymmetry between programmed and erased states as follows; vertical bar Q(FG)vertical bar exhibits the peak at similar to 100 cycles in programmed state, while vertical bar Q(FG)vertical bar monotonically reduces in erased state. Next, the midgap voltage (V-mid) shift of the cell caused by the generation of Q(OX) is also extracted by this method. Therefore, it enables to analyze the profiles of the hole and electron-trap separately across the oxide in detail. It is demonstrated that the hole-trap is mainly distributed near to Si surface and the centroid of electron-trap is located near to the middle of oxide. In addition, it is found that hole-trap near to Si has strong dependence on erase bias.