Browsing by Author "Chang, K. -Y."

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Near-threshold all-digital PLL with dynamic voltage scaling power management
(2016-01-21)
Chang, C. -W.
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Chang, K. -Y.
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Chu, Y. -H.
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Jou, S. -J.
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電子工程學系及電子研究所
A near-threshold all-digital phase-locked loop (ADPLL) with a power management unit (PMU) is presented to make the proposed ADPLL work reliably across variations and power consumption as well is reduced. When operated under near-threshold condition from 0.52 to 0.58 V V-DD, the gated digitally controlled oscillator frequency range is from 90.8 to 245.7 MHz. When the ADPLL is operated at 0.52 V V-DD, a lock-in time of 9.5 mu s at 100 MHz output clock frequency is measured with an rms period jitter of 0.17% UI. With the PMU, the ADPLL power reduction at 130 MHz output frequency is 39% and the buck converter power consumption is nearly 30 mu W. Consequently, the proposed ADPLL with PMU is suitable to event-driven or low-voltage applications.
Photoluminescence From InN Nanorod Arrays with a Critical Size
(2013-01-01)
Chang, K. -Y.
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Liu, Y. -S.
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Gwo, S.
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Ahn, H.
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光電工程學系
Abnormal temperature dependence of peak energy and bandwidth of photoluminescence spectra was observed for InN nanorods with a diameter <30 nm, which is of the same order of the thickness of surface electron accumulation layer.