Browsing by Author "Chang, K. C."

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A low-power current-reuse LNA for ultra-wideband wireless receivers from 3.1 to 10.6 GHz
(2007)
Kao, H. L.
;
Chin, Albert
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Chang, K. C.
;
McAlister, S. P.
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交大名義發表
We present an ultra-wideband 3.1-10.6 GHz low-noise amplifier which uses a two-stage current-reuse structure to reduce the power. Fabricated in a 0.18 mu m CMOS process, the IC prototype achieved a power gain of 9.3 dB, a noise figure (NF) of < 5.6 dB, an input match of < -8 dB over the band, while consuming only 9.4 mW.
Exploiting broad-area surface emitting lasers to manifest the path-length distributions of finite-potential quantum billiards
(2016-01-11)
Yu, Y. T.
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Tuan, P. H.
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Chang, K. C.
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Hsieh, Y. H.
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Huang, K. F.
Broad-area vertical-cavity surface-emitting lasers (VCSELs) with different cavity sizes are experimentally exploited to manifest the influence of the finite confinement strength on the path-length distribution of quantum billiards. The subthreshold emission spectra of VCSELs are measured to obtain the path-length distributions by using the Fourier transform. It is verified that the number of the resonant peaks in the path-length distribution decreases with decreasing the confinement strength. Theoretical analyses for finite-potential quantum billiards are numerically performed to confirm that the mesoscopic phenomena of quantum billiards with finite confinement strength can be analogously revealed by using broad-area VCSELs. (C) 2016 Optical Society of America
High-density nano-pillar SiOx-based resistive switching memory using nano-sphere lithography to fabricate a one diode - one resistor (1D-1R) architecture
(2014-01-01)
Chang, Y. F.
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Ji, L.
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Chen, Y. C.
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Zhou, F.
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Tsai, T. M.
A highly compact, one diode - one resistor (1D-1R) nano-pillar device architecture has been demonstrated using nano-sphere lithography (NSL) to fabricate SiOx-based resistive switching (RS) memory. The intrinsic SiOx-based resistive switching element and Si-based PN diode are self-aligned on the epitaxial silicon wafer using NSL and a deep-Si-etch process without using conventional photolithography. The DC electrical performance, an AC pulse response in the 50 ns regime, capability for multi-bit operation, and high readout margin immunity for sneak path issue demonstrate good potential for high-speed nonvolatile memory (NVM). The NSL fabrication process is an efficient, economical approach to enable large-scale patterning of 1D-1R architectures while providing excellent NVM performance for future applications.