Browsing by Author "Chang, KM"

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1.0 nm oxynitride dielectrics prepared by RTP in mixtures of N-2 and O-2 ambient
(2004)
Chang, KM
;
Yang, WC
;
Chen, CF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a reliable method of growing aggressively scaled, 1.0 nm thick, gate dielectric in mixtures of N-2 and O-2 ambient at 900degreesC for 15 s by rapid thermal processing (RTP). These oxynitride films have excellent interface properties, 100 times lower leakage current density, and better charge trapping properties than rapid thermal oxidation SiO2 of identical thickness prepared in pure O-2 ambient. The effect of interfacial nitrogen concentration on the device characteristics with gate oxynitride films grown in various N-2/O-2 gas flow ratios was also investigated. The results demonstrate that the uniform nitrogen content increases with the N-2/O-2 gas flow ratio and that high-quality oxynitride films can be obtained by RTP in an optimum gas flow ratio of N-2/O-2 = 5/1 (slm). (C) 2004 The Electrochemical Society.
A method to characterize n(+)-polysilicon/oxide interface traps in ultrathin oxides
(2001-06-01)
Chang, KM
;
Chung, YH
;
Lee, TC
;
Sun, YL
;
電子工程學系及電子研究所
In this study, a new method to characterize the n(+)-polysilicon/oxide interface trap state by measuring the gate voltage-gate leakage current (Vg-Jg) characteristics under the low electric field is developed. These traps are neutral and consist of the fast and slow trap states located near the Fermi level of the n(+)-polyoxide. We use the first order rate equation to characterize the relationship between the gate leakage current and the gate voltage sweep rate. A simple formula to characterize the detrapping behavior of the slow trap states with the detrapping time constant was derived. It is important to find that the smaller detrapping time constant observed in a thinner oxide (2.5 nm) is due to the field enhanced detrapping effect. (C) 2001 The Electrochemical Society.
A new BlueRing scatternet topology for Bluetooth with its formation, routing, and maintenance protocols
(2003-06-01)
Lin, TY
;
Tseng, YC
;
Chang, KM
;
資訊工程學系
;
Department of Computer Science
The basic networking unit in Bluetooth is piconet, and a larger-area Bluetooth network can be formed by multiple piconets, called scatternet. However, the structure of scatternets is not defined in the Bluetooth specification and remains as an open issue at the designers' choice. It is desirable to have simple yet efficient scatternet topologies with good supports of routing protocols, considering that Bluetooths are to be used for personal area networks with design goals of simplicity and compactness. In the literature, although many routing protocols have been proposed for mobile ad hoc networks, directly applying them poses a problem due to Bluetooth's special baseband and MAC-layer features. In this work, we propose an attractive scatternet topology called BlueRing, which connects piconets as a ring interleaved by bridges between piconets, and address its formation, routing, and topology-maintenance protocols. The BlueRing architecture enjoys the following fine features. First, routing on BlueRing is stateless in the sense that no routing information needs to be kept by any host once the ring is formed. This would be favorable for environments such as Smart Homes where computing capability is limited. Second, the architecture is scalable to median-size scatternets easily (e.g. around 50 similar to 70 Bluetooth units). In comparison, most star- or treelike scatternet topologies can easily form a communication bottleneck at the root of the tree as the network enlarges. Third, maintaining a BlueRing is an easy job even as some Bluetooth units join or leave the network. To tolerate single-point failure, we propose a protocol-level remedy mechanism. To tolerate multipoint failure, we propose a recovery mechanism to reconnect the BlueRing. Graceful failure is tolerable as long as no two or more critical points fail at the same time. As far as we know, the fault-tolerant issue has not been properly addressed by existing scatternet protocols yet. In addition, we also evaluate the ideal network throughput at different BlueRing sizes and configurations by mathematical analysis. Simulation results are presented, which demonstrate that BlueRing outperforms other scatternet structures with higher network throughput and moderate packet delay. Copyright (C) 2003 John Wiley Sons, Ltd.
A new fabrication technique for silicon nanowires
(2004-06-01)
Sheu, JT
;
Kuo, JM
;
You, KS
;
Chen, CC
;
Chang, KM
A new method is proposed for fabricating silicon nanowires (SiNWs) on silicon substrates instead of on SOI wafers, providing a cheaper process; it also enables their electrical properties to be measured easily. Using scanning probe lithography, mask patterns for SiNWs were defined on a (110)-oriented bare silicon wafer. Subsequently silicon nitride spacers were produced and utilized to protect SiNWs during a dry-oxidation process, which was applied to isolate the SiNWs from the substrate. The field induced oxide mask patterns generated with a scanning probe microscope were around 50-60 mn in width, and SiNWs with 34 nm in width and 160 nm in height resulted after wet potassium hydroxide (KOH) orientation-dependent etching at 40degrees for 400 s. SiNWs with line width around 34 mn on the bare silicon wafer were achieved with the scanning probe lithography process and conventional IC processing. (C) 2004 Elsevier B.V. All rights reserved.
A new simple and reliable method to form a textured Si surface for the fabrication of a tunnel oxide film
(1998-05-01)
Chang, KM
;
Li, CH
;
Sheih, BS
;
Yang, JY
;
Wang, SW
In this work, a textured Si surface was formed with a new simple and reliable method for tunnel oxide fabrication. First, a thin poly-Si layer (12 nm thick) was deposited on Si surface and a 30-nm thick dry oxide film was then grown in O-2 ambient. This oxide film was served as a sacrificial oxide. The poly-Si film and Si substrate were both oxidized during thermal oxidization. After stripping this sacrificial oxide, a textured Si surface was obtained. Tunnel oxide grown on this textured Si surface has an asymmetrical J-E characteristics, less interface states generation and better reliability (larger Q(bd)) as compared to those of normal oxide.
A new small-signal MOSFET model and parameter extraction method for RF IC's application
(2004-09-01)
Chang, KM
;
Wang, HP
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, an accurate and simple small signal model of RF MOSFETs accounting for the distributed gate effect, the substrate parasitics and charge conservation is proposed. Meanwhile, a direct and accurate extraction method using linear regression approach for the components of the equivalent circuit of the MOSFET with S-parameters analysis is also proposed. The proposed model and extraction method are verified with the experimental data and an excellent agreement is obtained up to 10 GHz. The extraction results from the measured data for various bias conditions are presented. Also, the extracted parameters, such as transconductance g(m), match well with those obtained from DC measurements. Besides, it is shown that a significant error in circuit performances would be found if the charge conservation is not properly considered. (C) 2004 Elsevier Ltd. All rights reserved.
A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions
(2001-10-01)
Chang, KM
;
Chung, YH
;
Lin, GM
;
Lin, JH
;
Deng, CG
In this letter, a novel high-performance poly-silicon thin-film transistor (poly-Si TFT) with a self-aligned thicker sub-gate oxide near the drain/source regions is proposed. Poly-Si TFTs with this new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9 x 10(6) and also shows the off-state leakage current 100 times lower than those of the conventional ones at V-GS = -15 V and V-DS = 10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications.
A novel pretreatment technology for organic low-dielectric material to suppress copper diffusion and improve ashing resistance
(2000-06-01)
Chang, KM
;
Deng, IC
;
Tsai, YP
;
Wen, CY
;
Yeh, SJ
new novel pretreatment technology for integration of organic low-dielectric material in copper interconnects for ultralarge scale integration applications is developed. Using NH3 plasma treatment, two extremely important advantages were achieved in spin-on organic polymer (SOP), including the reduction of copper diffusion and the improvement of ashing resistance. A copper/SOP/Si capacitor structure is used to study the electrical characteristics of SOP film after ashing treatment or postanneal. Higher barrier capability and better ashing resistance can be achieved by the SOP layer after NH3 plasma treatment. After annealing at 500 degrees C for 60 min, secondary ion mass spectroscopy depths profile shows that the Cu atoms do not penetrate into the SOP when they are pretreated by NH3 plasma. Furthermore after the ashing step, the carbon atoms in the SOP film almost remain the same when they are pretreated by NH3 plasma. On the other hand, the concentration of carbon in as-cured SOP is no longer seen. The reason of improving ashing resistance and better barrier capability was due to the organic polymer film rearranging to form a carbon-containing silicon nitride film. (C) 2000 The Electrochemical Society. S0013-4651(99)10-007-7. Ail rights reserved.
A novel process and thermodynamic mechanisms of air gap formation for ULSI application
(2000-11-01)
Chang, KM
;
Yang, JY
;
Chen, LW
;
Tseng, MH
;
電子工程學系及電子研究所
In this study, a novel process to fill the gap between the metal lines on a wafer with air is developed. Reduction of the parasitic wire capacitance in ULSI has become an important issue for future high-speed and low-power applications. Use of low dielectric constant material as inter-level dielectric (ILD) can overcome this problem. Many new low dielectric constant materials are under study and lower dielectric constant and feasibility are the two goals of these researches. The gas-dielectric process has the lowest dielectric constant, 1.0, and its conceptual feasibility is demonstrated. Basic process characterization data, thermodynamic mechanism and requirements for air gap formation are also discussed. We calculated the relationship among the surface tension, the vaporization rate and atmospheric pressure to construct a model of the process window to show that this process is feasible and reproducible. Scanning electron microscope data show that a large area of air gap can be obtained. Basic electrical characteristics data such as I-V and C-V, measured and compared with the conventional PECVD process, show that the air gap has better isolation than PECVD process. (C) 2000 Elsevier Science S.A. All rights reserved.
A novel technology to form air gap for ULSI application
(1999-04-01)
Chang, KM
;
Yang, JY
;
Chen, LW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, we develop a novel process to fill the interline space with air (dielectric constant = 1). A silicon wafer, whose face is downward, patterned with metal lines, is placed on the top of another silicon wafer coated with dry polyimide. Hydrogen silsesquioxanes (HSQ), FOx-16, is diluted and trickled through the slit between the metal lines and the polyimide. Then the HSQ forms an ultrathin liquid layer on the dry polyimide and contacts with the top of the metal lines. After the liquid HSQ becomes dry, the air gap is formed, The dry polyimide has good adhesion to silicon substrate but not to the dry FOx-16, so we can separate the polyimide from the dry FOx-16 and get the air gap. The liquid property of HSQ and its high selective adsorption between the metal lines and the polyimide are utilized to form the air gap.
A pretreatment technique to improvement the ashing resistance of low k spin-on-polymer (SOP)
(1999)
Chang, KM
;
Yang, JY
;
Chang, YH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The oxygen plasma via resists strip process cause significant damage to organic SOP, thus limiting its inter-level dielectric application. A simple treatment technology using reactive ion is proposed to reform the SOP surface. The reactive ion modification of the SOP can improve the resistance towards oxygen plasma. This is owing to the carbon atom absence in the SOP's surface area. The measurements of Fourier transform infrared (FTIR) spectroscopy, x-ray photoelectron spectroscopy (XPS), stress, thickness variation, Scanning Electron Microscope (SEM) cross-sectional view for gap filling and dielectric constant show that SOP with reactive ion treatment (RIT) has better quality for non-etch-back process than SOP without RIT.
A simple 2D analytical threshold voltage model for fully depleted short-channel silicon-on-insulator MOSFETs
(2004-12-01)
Chang, KM
;
Wang, HP
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose a simple two-dimensional (2D) analytical threshold voltage model for deep-submicrometre fully depleted SOI MOSFETs using the three-zone Green's function technique to solve the 2D Poisson equation and adopting a new concept of the average electric field to avoid iterations in solving the position of the minimum surface potential. Firstly, we obtain the 2D potential distribution in the Si-film region by using the Green's function technique to solve the 2D Poisson equation. Then, by applying Gauss's law at the Si-SiO2 interface, the initial expression of the threshold voltage is obtained. Eventually, we introduce a modified factor to compensate for the errors resulting from the charge-sharing effect in the derivations of the final threshold voltage model. The proposed model is validated against the results obtained by 2D numerical analysis and experimental data, and excellent agreements are obtained. The proposed model has an explicit expression and can be implemented into the circuit simulator.
Amorphouslike chemical vapor deposited tungsten diffusion barrier for copper metallization and effects of nitrogen addition
(1997-08-01)
Chang, KM
;
Yeh, TH
;
Deng, IC
;
Shih, CW
;
電子工程學系及電子研究所
In this article, we propose an amorphouslike chemical vapor deposited tungsten (CVD-W) thin him as a diffusion barrier for copper metallization. Experimental results gave no evidence of interdiffusion and structural change for Cu/amorphouslike CVD-W/Si samples annealed up to 675 degrees C for 30 min in N-2. At higher temperatures (700 degrees C), Cu penetration results in the formation of eta ''-Cu3Si precipitates at the CVD-W/Si interface. This is due to the crystallization of the amorphouslike CVD-W film above 650 degrees C, rendering the grain-boundary structure and, hence, fast pathways for Cu diffusion. The Cu/amorphouslike CVD-W/p(+)n diodes, thus, sustain large increases in reverse leakage current. In addition, the effects of nitrogen addition by using an in situ nitridation on the amorphouslike CVD-W film are also discussed. The effectiveness of the nitrided barrier is attributed to the blocking of the grain boundaries in the tungsten film by nitrogen atoms. This slows down Cu diffusion significantly. Physical and chemical analyses indicate that interfaces in the Cu/WNx/W/Si multilayer maintain their integrity while the annealing is carried out at 750 degrees C. Moreover, the reverse leakage current densities of Cu/WNx/W/p(+)n diodes remain at 10(-7) A/cm(2) after 725 degrees C annealing. (C) 1997 American Institute of Physics.
Amorphouslike chemical vapor deposited tungsten diffusion barrier for copper metallization and effects of nitrogen addition
(1997-08-01)
Chang, KM
;
Yeh, TH
;
Deng, IC
;
Shih, CW
;
電子工程學系及電子研究所
In this article, we propose an amorphouslike chemical vapor deposited tungsten (CVD-W) thin him as a diffusion barrier for copper metallization. Experimental results gave no evidence of interdiffusion and structural change for Cu/amorphouslike CVD-W/Si samples annealed up to 675 degrees C for 30 min in N-2. At higher temperatures (700 degrees C), Cu penetration results in the formation of eta ''-Cu3Si precipitates at the CVD-W/Si interface. This is due to the crystallization of the amorphouslike CVD-W film above 650 degrees C, rendering the grain-boundary structure and, hence, fast pathways for Cu diffusion. The Cu/amorphouslike CVD-W/p(+)n diodes, thus, sustain large increases in reverse leakage current. In addition, the effects of nitrogen addition by using an in situ nitridation on the amorphouslike CVD-W film are also discussed. The effectiveness of the nitrided barrier is attributed to the blocking of the grain boundaries in the tungsten film by nitrogen atoms. This slows down Cu diffusion significantly. Physical and chemical analyses indicate that interfaces in the Cu/WNx/W/Si multilayer maintain their integrity while the annealing is carried out at 750 degrees C. Moreover, the reverse leakage current densities of Cu/WNx/W/p(+)n diodes remain at 10(-7) A/cm(2) after 725 degrees C annealing. (C) 1997 American Institute of Physics.
An alternative process for silicon nanowire fabrication with SPL and wet etching system
(2004)
Chang, KM
;
You, KS
;
Lin, JH
;
Sheu, JT
;
電子工程學系及電子研究所
Silicon nanowire fabrication of nanoscale dimensions on a single-crystal silicon surface by scanning probe lithography (SPL) and potassium hydroxide (KOH) aqueous wet etching system has proven to be adequate technological processes. Using SPL directly to define patterns on a single-crystal silicon surface showed that the linewidth of similar to50 nm can be further shrunk to similar to20 nm with KOH wet etching and orientation-dependent etching (ODE) processes on (110)-oriented silicon samples. In addition, this lithography technique also showed a great ability to define patterns on fluorocarbon mask layers. This method performed the fine linewidth of silicon nanowires around 20 nm by operating with lower applied voltages and higher scanning speeds (shorter exposure time) with SPL and ODE techniques and KOH wet etching on (100)-oriented silicon samples. These alternative processes provide the capability to fabricate nanoscale structures with high reliability and repeatablility for applications in the nanofields. (C) 2004 The Electrochemical Society.
An investigation of inner light during Zen meditation using alpha-suppressed EEG and VEP
(2005)
Chang, KM
;
Liu, CY
;
Lo, PC
;
電控工程研究所
;
Institute of Electrical and Control Engineering
Sensitivity to light is a common experience during prayer or Zen meditation, in both western and eastern cultures. Higher levels of happiness and lower health insurance costs are typical for those who experience inner tight. In this report, the connection between the experience of inner light and Zen meditation is investigated by using EEG and flash visual evoked potential (F-VEP) recorded from the occipital site Oz. EEG results indicate that the experience of inner light during Zen meditation by experienced practitioners is also accompanied by a large amount of alpha-suppressed EEG. The F-VEP data also reflect shorter latency, and indicates a stronger and more sensitive visual response during Zen meditation. These data are also the typical physiological responses when the eyes are open during a rested conscious state, and thus provide a possible closer connection between Zen meditation and the sensitivity of inner light.
Anomalous variations of OFF-state leakage current in poly-Si TFT under static stress
(2002-05-01)
Chang, KM
;
Chung, YH
;
Lin, GM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, we study the anomalous variations of the OFF-state leakage current (I-OFF) in n-channel poly-Si thin-film transistors (TFTs) under static stress. The dominant mechanisms for the anomalous I-OFF can be attributed to 1) I-OFF increases due to channel hot electrons trapping at the gate oxide/channel interface and silicon grain boundaries and 2) I-OFF decreases due to hot holes accumulated/trapped near the channel/bottom oxide interface near the source region. Under the stress of high drain bias, serious impact ionization effect will occur to generate hot electrons and hot holes near the drain region. Some of holes will be injected into the gate oxide due to the vertical field (similar to(V_stress - V_ - Dstress) /T-ox) near the drain and the others will be migrated from drain to source along the channel due to lateral electric field (similar toV_Dstress/L-CH).
Barrier characteristics of chemical vapor deposited amorphous-like tungsten silicide with in situ nitrogen plasma treatment
(1999-07-01)
Chang, KM
;
Deng, IC
;
Yeh, TH
;
Shih, CW
;
電子工程學系及電子研究所
Our team investigated the characteristics of inserting an 80 nm amorphous-like WSi1.6N0.5N/WSi1.6 barrier layer between aluminum film and a shallow diode to retard aluminum and silicon interdiffusion. In one chamber without breaking vacuum, we used a nitrogen plasma treatment to stuff nitrogen atoms into the grain boundaries of amorphous-like tungsten silicide film. The nitrogen atoms eliminated the fast diffusion paths of film, thus giving the amorphous-like tungsten silicide film a smaller diffusion coefficient. We then examined the failure of diodes with amorphous-like WSi1.6N0.5/WSi1.6 barriers which were annealed at 575 degrees C for 30 min and which had leakage currents of 10(7) and 10(8) nA/cm(2). These diodes failed due to the diffusion of aluminum along the sidewalls of the barriers and the field oxide interface. In the search for a solution to this problem we investigated the use of tetraethylorthosilicate, which is known for its thermal stability as a stress buffer. In this experiment we used tetraelhylorthosilicate to form a "contact array structure" which in turn prevented diode failure at 575 degrees C annealing for 30 min, and furthermore, the diodes in the contact array structure only began to show evidence of degradation at 600 degrees C. (C) 1999 The Electrochemical Society. S0013-4651(98)09-086-7. All rights reserved.
Brightness enhancement of ITO/GaN LEDs by self-aligned micro-net structures
(2005)
Chang, KM
;
Chu, JY
;
Cheng, CC
;
Chu, CF
;
電子工程學系及電子研究所
Arrays of square and hexagonal holes of various dimensions were patterned on indium-tin-oxide (ITO)/GaN light-emitting diodes (LEDs) using the self-aligned method to increase the light extraction area and shorten the optical paths. The hole region was etched to give the sidewall of the active layer a sloped profile, and it was passivated by SiOxNy films to extract more light. The self-aligned micro-net LED is at least 10% brighter than the conventional structure in the normal direction without loss of operating voltage or leakage current. The ratio of luminescence to total output power is increased by 25% at a current density of 100 A/cm(2). Moreover, varying the hole dimensions and the designed density increased the peak external quantum efficiency by 5% at a current of 3 mA. The greater axial luminescence and the higher external quantum efficiency make LEDs self-aligned micro-net structures quite useful in surface-mounting and low-power-consuming devices, such as cellular phones. (c) 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Characteristics of N2O-grown polyoxide by the recrystallized-polysilicon method
(1998-12-01)
Chang, KM
;
Lee, TC
;
Sun, YL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work proposes a new method for growing the polyoxide and investigates its characteristics. Thin amorphous silicon was deposited on the first polysilicon and then recrystallized at 600 degrees C for 24 h to form a new polysilicon. The N2O-grown polyoxide formed by this method has a higher conduction current and better stress endurance than those of the conventional polyoxide. The higher quality polyoxide, as measured by lower gate voltage shift and larger charge-to-breakdown (Q(bd)), is due to the smooth polyoxide/polysilicon interface which increases the stress endurance under high fields. (C) 1998 The Electrochemical Society. S1099-0062(98)06-105-7. All rights reserved.