Browsing by Author "Chang, Kuo-Chiang"

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10-ms 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank for Digital Hearing Aids
(2013-03-01)
Liu, Chih-Wei
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Chang, Kuo-Chiang
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Chuang, Ming-Hsun
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Lin, Ching-Hao
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電子工程學系及電子研究所
The ANSI S1.11 1/3-octave filter bank is suitable for digital hearing aids, but its large group delay and high computational complexity complicate matters considerably. This study presents a 10-ms 18-band quasi-ANSI S1.11 1/3-octave filter bank for processing 24 kHz audio signals. We first discuss a filter order optimization algorithm to define the quasi-ANSI filters. The group delay constraint of filters is limited to 10 ms. The proposed design adopts an efficient prescription-fitting algorithm to reduce inter-band interference, enabling the proposed quasi-ANSI filter bank to compensate any type of hearing loss (HL) using the NAL-NL1 or HSE prescription formulas. Simulation results reveal that the maximum matching error in the prescriptions of the mild HL, moderate HL, and severe-to-profound HL is less than 1.5 dB. This study also investigates the complexity-effective multirate IFIR quasi-ANSI filter bank. For an 18-band digital hearing aid with a 24 kHz sampling rate, the proposed architecture eliminates approximately 93% of the multiplications and up to 74% of the storage elements, compared with a parallel FIR filters architecture. The proposed analysis filter bank (AFB) was designed in UMC 90 nm CMOS high-VT technology, and on the basis of post-layout simulations, it consumes 73 mu W (@V-DD = 1 V). By voltage scaling (to 0.6 V), the simulation results show that the power consumption decreases to 27 mu W, which is approximately 30% of that consumed by the most energy-efficient AFB available in the literature for use in hearing aids.
A Low Power Hearing Aid Computing Platform Using Lightweight Processing Elements
(2012)
Chang, Kuo-Chiang
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Chen, Yu-Wen
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Kuo, Yu-Ting
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Liu, Chih-Wei
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電子工程學系及電子研究所
This paper presents a power-efficient computing platform for hearing aids. The proposed platform composes four heterogeneous processing elements. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerators. The hardwired accelerators integrate static floating-point and truncated multiplier to improve signal-to-noise ratio and reduce computational complexity. Compared to the post-truncate multiplication in FIR filter, the proposed static floating-point datapath reduces 50.8% area and improves 2.2 dB SNR simultaneously.
A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor
(2016-04)
Liu, Chih-Wei
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Ou, Shih-Hao
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Chang, Kuo-Chiang
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Lin, Tzung-Ching
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Chen, Shin-Kai
Based on an error-flattened, non-uniform-region linear-approximation algorithm, this brief proposes a low-error and a cost-efficient design procedure for realizing an optimized shift-and-add Logarithmic Unit (LU), which uses minimum hardware to meet the desired error constraint for embedded graphics systems. Mathematically, this brief first derives two solutions of the error-flattened algorithm. Subsequently, for an error constraint, the minimum number of approximation regions, n, the corresponding i th interpolation coefficients (a(i), b(i)), and the regional endpoints (x(i-1), x(i)), 1 <= i <= n, are obtained accordingly. Using the unique properties of the logarithmic function, spacing of x(i) is non-uniform to make errors in each region consistent. Carefully examining the cost of the applied add/sub network, a low-cost candidate for a shift-and-add LU is determined. Next, a cost exploration process, which gradually increases n, is performed. A large number of regions results in a more accurate conversion algorithm that might tolerate more implementation errors by using simple hardware whose cost is lower than that of the inferior candidate. After exploring the cost based on error tolerance, the proposed design procedure finally generates a hardware to meet the desired error constraint. Slightly modifying the regional endpoint x(i) increases hardware efficiency at the cost of increased error. Proposed circuits were synthesized in UMC 65RVT CMOS technology. Compared to state-of-the-art shift-and-add logarithmic converters, simulation results reveal that the proposed design saves approximately 12.7-51.1 percent area of polynomial approximation and improves approximately 1-14-dB SNR gain while achieving a tighter error constraint.
A Variable-Latency, Ultra-Low-Voltage RISC Processor with a New In-Situ Error Detection and Correction Technique
(2016)
Lin, Chi-Chun
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Chang, Kuo-Chiang
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Liu, Chih-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
To overcome significant PVT variation in ultra low -voltage (LTV) operation, a new in-situ error detection and recovery mechanism is proposed to optimize circuit design for typical-case. The proposed technique detects glitch of a (ctitical-path) circuit output within the setup-time duration of a flip-flop and stalls the clock source, if possible, until the output is stable once an error is detected. Applying the proposed in-situ error detection, a test chip of an ULV 32-bit simple RISC with a 128-point FFT has been implemented with TSMC 40 nm CMOS process. The chip\'s measurement results confirms the functional correctness of the proposed in-situ error detection mechanism. Comparing that with the simple RISC with conventional worst case design principle, the proposed variable-latency ULV one reduces approximately 46% energy dissipation. And, with the similar energy consumption, the proposed PIN RISC achieves approximately 1.16 times throughput improvement.
An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids
(2015-01-01)
Ou, Shih-Hao
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Chang, Kuo-Chiang
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Liu, Chih-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The main contribution of this study is the development of an area-/energy-efficient cascaded direct-truncation (DT) datapath with the so-called static floating-point (SFP) arithmetic to realize a low-delay analysis filter bank (AFB) for digital hearing aids. In the proposed SFP LPFIR (linear-phase finite impulse response) filter engine, lower silicon area and lesser power consumption facilitate better SNR performance than that achieved with the conventional post-truncation (PT) datapath with integer arithmetic. Moreover, in the proposed LPFIR filter engine, a cascaded 16-bit SFP A-M-S-Acc datapath is used that consists of two embedded 1-bit shifters to improve hardware usage and parallelism, one 16-bit DT adder (A), one 16-bit DT multiplier (M), one 16-bit barrel shifter (S), and one 16-bit DT accumulator (Acc). The operations per cycle (OPC) of the proposed SFP LPFIR filter engine reaches 6, which enables efficient fabrication of the low-latency AFB for hearing aids. To verify the effectiveness of the proposed 16-bit SFP LPFIR filter engine, a 10-ms 18-band quasi-ANSI S1.11 1/3-octave AFB for digital hearing aids was implemented using UMC 90-nm CMOS technology. The AFB was operated at 792 kHz to process, in real-time, 24 kHz audio, with the power consumption being approximately 80.6 mu W (at 1 V). Compared to the previous design in which the conventional PT datapath with integer arithmetic was used, approximately 9.6% of total power and 83% of silicon area were saved and almost the same SNR (signal-to-noise ratio) performance was achieved with the new system, when evaluated by a 3.96-s sequence of Mandarin speech. (C) 2014 Elsevier B.V. All rights reserved.
An Ultra-Low Voltage Hearing Aid Chip using Variable-Latency Design Technique
(2014-01-01)
Chang, Kuo-Chiang
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Luo, Shien-Chun
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Huang, Ching-Ji
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Liu, Chih-Wei
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Chu, Yuan-Hua
This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 mu W at 0.5V and 6 MHz.
Complexity-Effective Auditory Compensation with a Controllable Filter for Digital Hearing Aids
(2012)
Chang, Ya-Ting
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Chang, Kuo-Chiang
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Kuo, Yu-Ting
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Liu, Chih-Wei
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電子工程學系及電子研究所
Auditory compensation consumes significant power due to the computation-intensive operations in the filter bank. To reduce the complexity, a controllable filter was designed to replace the filter bank. Filter order was designed to match prescriptions within a specific error constraint with minimum computational cost. An interpolation scheme according to the variation of signal intensity was implemented to reduce the overhead of coefficients calculations. The proposed auditory compensation reduces 80% of multiplications and 30% of power consumption compared to the complexity-effective multi-rate filter bank architecture [4]. Moreover, the group delay was also reduced from 10 ms to 2.4 ms.
Complexity-Effective Dynamic Range Compression for Digital Hearing Aids
(2010)
Chang, Kuo-Chiang
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Kuo, Yu-Ting
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Lin, Tay-Jyi
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Liu, Chih-Wei
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電子工程學系及電子研究所
Dynamic range compression (DRC) is an essential function in digital hearing aids, which have stringent power consumption constraints. This work minimized the complexity of the DRC algorithm through adopting functional approximation for those involved nonlinear operations. The tradeoff between computation reduction and approximation error was explored for reducing hardware cost without introducing audible artifact. Moreover, finite wordlength analysis is conducted for the wordlength minimization and further complexity saving. The experimental result shows that our design totally reduces 96% computing complexity of the straightforward implementation without introducing audible difference in the output signals. Compared with other approximation methods, our design also requires lower hardware complexity.
Complexity-Effective Implementation of Programmable FIR Filters Using Simplified Canonic Signed Digit Multiplier
(2014-01-01)
Chang, Kuo-Chiang
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Lin, Ching-Hao
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Liu, Chih-Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an energy-efficient FIR filter architecture which applies CSD multiplication to satisfy the design considerations of power consumption, flexibility and area cost. The proposed architecture reduces number of partial product rows and shift range of each coefficient multiplication to reduce energy consumption. However, the simplification restricts the use of filter coefficients. To mitigate this problem, this paper also presents a coefficient pre-processing flow to transform the original coefficients into applicable ones at design time to meet the restriction of the proposed multiplier. The simulation result reveals this technique can be applied for the computation of 97-tap filter. The design reduces up to 21.5% energy consumption per sample when compared with conventional Booth multiplier.
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells
(2014-12-01)
Luo, Shien-Chun
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Chang, Kuo-Chiang
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Chen, Ming-Pin
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Huang, Ching-Ji
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Chiu, Yi-Fang
This brief presents an implementation of ultralow-power microcontrollers that use a separate clock network voltage (SCNV) to correct unexpected errors produced by on-chip variations (OCVs). Separating the clock network voltage requires amendments in the standard cell library and physical designs. Here, the experiments used a 65-nm technology that exhibited considerable OCVs, which caused write and retention errors in clocked storage cells and limited the voltage scaling of microcontrollers. Using the SCNV provides an extraordinary operability to correct errors in the low-voltage clocked storage cells. In addition, the area overhead of the proposed implementation is negligible. Applying the SCNV, the measurement results indicate that the microcontrollers can be operated below 0.3 V, over 0.15-V extension in voltage scaling, and achieve the optimal energy consumption at 0.34 V. Separating the clock network voltage has tradeoff issues in system timing and energy consumption based on the measurement results, and this brief discusses proper applications.
SPATIAL-CUE-BASED MULTI-BAND BINAURAL NOISE REDUCTION FOR HEARING AIDS
(2013)
Yang, Cheng-Yen
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Chou, Wen-Sheng
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Chang, Kuo-Chiang
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Liu, Chih-Wei
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Chi, Tai-Shih
A noise reduction algorithm for binaural hearing aids is proposed in this paper. The proposed algorithm suppresses the directional interferences and diffuse noise using the interaural time difference (ITD), interaural level difference (ILD) and interaural coherence cues via the time-frequency (T-F) masking process. Furthermore, the proposed algorithm is evaluated under different specifications of ANSI-like filter banks for comprehending dominant factors in boosting the de-noise performance. Experimental results suggest that a higher resolution in low frequencies (approximately less than 1000 Hz) and a higher overlapping ratio of the filters are beneficial to de-noise performance in terms of sound quality.