Browsing by Author "Chang, Li-Pin"

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A Hybrid Approach to NAND-Flash-Based Solid-State Disks
(2010-10-01)
Chang, Li-Pin
;
資訊工程學系
;
Department of Computer Science
Replacing power-hungry disks with NAND-flash-based solid-state disks (SSDs) is a recently emerging trend in flash-memory applications. One important SSD design issue is achieving a good balance between cost, performance, and lifetime. This study introduces a hybrid approach to large SSDs that combines MLC NAND flash and SLC NAND flash. Each of these flash architectures has its own drawbacks and benefits, and this study proposes that the two can complement each other. However, there are technical challenges pertaining to data placement, data migration, and wear leveling in heterogeneous NAND flash. The experimental results of our study show that combining 256 MB SLC flash with 20 GB MLC flash produces a hybrid SSD. This hybrid SSD is 1.8 times faster than a purely MLC-flash-based SSD in terms of average response time and improves energy consumption by 46 percent. The proposed hybrid SSD costs only four percent more than a purely MLC-flash-based SSD. The extra cost of a hybrid SSD is very limited and rewarding.
A Hybrid Approach to NAND-Flash-Based Solid-State Disks
(2010-10-01)
Chang, Li-Pin
;
資訊工程學系
;
Department of Computer Science
Replacing power-hungry disks with NAND-flash-based solid-state disks (SSDs) is a recently emerging trend in flash-memory applications. One important SSD design issue is achieving a good balance between cost, performance, and lifetime. This study introduces a hybrid approach to large SSDs that combines MLC NAND flash and SLC NAND flash. Each of these flash architectures has its own drawbacks and benefits, and this study proposes that the two can complement each other. However, there are technical challenges pertaining to data placement, data migration, and wear leveling in heterogeneous NAND flash. The experimental results of our study show that combining 256 MB SLC flash with 20 GB MLC flash produces a hybrid SSD. This hybrid SSD is 1.8 times faster than a purely MLC-flash-based SSD in terms of average response time and improves energy consumption by 46 percent. The proposed hybrid SSD costs only four percent more than a purely MLC-flash-based SSD. The extra cost of a hybrid SSD is very limited and rewarding.
A Locality-Preserving Write Buffer Design for Page-Mapping Multichannel SSDs
(2014)
Huang, Sheng-Min
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Chang, Li-Pin
;
資訊工程學系
;
Department of Computer Science
Advanced SSDs employ a RAM-based write buffer to improve their write performance. The buffer intentionally delays write requests in order to reduce flash write traffic and reorders them to minimize the cost of garbage collection. This work presents a novel buffer algorithm for page-mapping multichannel SSDs. We propose grouping temporally or spatially correlated buffer pages and writing these grouped buffer pages to the same flash block. This strategy dramatically increases the probability of bulk data invalidations in flash blocks. In multichannel architectures, channels are assigned to their own groups of buffer pages for writing, and so channel striping does not divide a group of correlated buffer pages into small pieces. We have conducted simulations and experiments using a SSD simulator and a real SSD platform, respectively. Our results show that our design greatly outperforms existing buffer algorithms.
A Low-Cost Wear-Leveling Algorithm for Block-Mapping Solid-State Disks
(2011-01-01)
Chang, Li-Pin
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Huang, Li-Chun
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資訊工程學系
;
Department of Computer Science
Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. However, flash lifetime is becoming a critical issue in the popularity of solid-state disks. Wear-leveling methods can prevent flash-storage devices from prematurely retiring any portions of flash memory. The two practical challenges of wear-leveling design are implementation cost and tuning complexity. This study proposes a new wear-leveling design that features both simplicity and adaptiveness. This design requires no new data structures, but utilizes the intelligence available in sector-translating algorithms. Using an on-line tuning method, this design adaptively tunes itself to reach good balance between wear evenness and overhead. A series of trace-driven simulations show that the proposed design outperforms a competitive existing design in terms of wear evenness and overhead reduction. This study also presents a prototype that proves the feasibility of this wear-leveling design in real solid-state disks.
A Low-Cost Wear-Leveling Algorithm for Block-Mapping Solid-State Disks
(2011)
Chang, Li-Pin
;
Huang, Li-Chun
;
資訊工程學系
;
Department of Computer Science
Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. However, flash lifetime is becoming a critical issue in the popularity of solid-state disks. Wear-leveling methods can prevent flash-storage devices from prematurely retiring any portions of flash memory. The two practical challenges of wear-leveling design are implementation cost and tuning complexity. This study proposes a new wear-leveling design that features both simplicity and adaptiveness. This design requires no new data structures, but utilizes the intelligence available in sector-translating algorithms. Using an on-line tuning method, this design adaptively tunes itself to reach good balance between wear evenness and overhead. A series of trace-driven simulations show that the proposed design outperforms a competitive existing design in terms of wear evenness and overhead reduction. This study also presents a prototype that proves the feasibility of this wear-leveling design in real solid-state disks.
A real-time configurable synchronization protocol for self-suspending process sets
(2009-08-01)
Chen, Ya-Shu
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Chang, Li-Pin
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資訊工程學系
;
Department of Computer Science
While several of researchers have proposed excellent protocols on resource synchronization, little work has been done for processes that might suspend themselves for I/O access, especially when they tend to be more tolerant to multiple priority inversions. This paper presents research results extended from the concept of priority ceilings with the objective of satisfying different priority-inversion requirements for different processes. We aim at practical considerations in which processes might voluntarily give up CPU and be willing to receive more blocking time than those in more traditional approaches. Extensions on the proposed scheduling protocols for deadlock prevention are also considered.
A Self-Balancing Striping Scheme for NAND-Flash Storage Systems
(2008)
Chang, Yu-Bin
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Chang, Li-Pin
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資訊工程學系
;
Department of Computer Science
To use multiple memory banks in parallel is a nature approach to boost the performance of flash-memory storage systems. However, realistic data-access localities unevenly load each memory bank and thus the benefits of parallelism is severely limited. In this work, we propose to encode popular data with redundancy by means of erasure codes. Load balancing is thus achieved by accessing only lightly loaded banks, because to retrieve a subset of data blocks and code blocks sufficiently reconstructs the requested data. The technical issues pertain to redundancy allocation, redundancy placement, and request scheduling. By experiments, we found that, by offering 10% extra redundant space, the read response time is largely improved by 30%.
Adaptive Write Interference Management with Efficient Mapping for Shingled Recording Disks
(2019-01-01)
Lee, Ming-Chang
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Chang, Li-Pin
;
Wu, Sung-Ming
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Yui, Wei-Shang
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資訊工程學系
Shingled Magnetic Recording (SMR) is a novel disk technology that partially overlaps adjacent disk tracks for high storage density. The partial overlap creates write interference between tracks, and overwriting a track requires to rewrite all its downstream tracks. Inspired by the highly unequal track modify probabilities under real workloads, we propose moving frequently modified tracks toward a downstream, deliberately reserved track, called a guard track, to reduce the extent of write interference. We also introduce a low-cost, seek-optimized scheme for efficient logical-to-physical address mapping. Experimental results showed that our approach outperformed a popular design by 54% and 55% on average in terms of write response time and total disk writes, respectively.
An Adaptive, Low-Cost Wear-Leveling Algorithm for Multichannel Solid-State Disks
(2013-12-01)
Chang, Li-Pin
;
Chou, Tung-Yang
;
Huang, Li-Chun
;
資訊工程學系
;
Department of Computer Science
Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. As flash memory endures only limited program-erase cycles, solid-state disks employ wear-leveling methods to prevent any portions of flash memory from being retired prematurely. Modern solid-state disks must consider wear evenness at both block and channel levels. This study first presents a block-level wear-leveling method whose design has two new ideas. First, the proposed method reuses the intelligence available in flash-translation layers so it does not require any new data structures. Second, it adaptively tunes the threshold of block-level wear leveling according to the runtime write pattern. This study further introduces a new channel-level wear-leveling strategy, because block-level wear leveling is confined to a channel, but realistic workloads do not evenly write all channels. The proposed method swaps logical blocks among channels for achieving an eventually-even state of channel lifetimes. A series of trace-driven simulations show that our wear-leveling method outperforms existing approaches in terms of wear evenness and overhead reduction.
An anomaly prevention approach for real-time task scheduling
(2009-01-01)
Chen, Ya-Shu
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Chang, Li-Pin
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Kuo, Tei-Wei
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Mok, Aloysius K.
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資訊工程學系
This research responds to practical requirements in the porting of embedded software over platforms and the well-known multiprocessor anomaly. In particular, we consider the task scheduling problem when the system configuration changes. With mutual-exclusive resource accessing, we show that new violations of the timing constraints of tasks might occur even when a more powerful processor or device is adopted. The concept of scheduler stability and rules are then proposed to prevent scheduling anomaly from occurring in task executions that might be involved with task synchronization or I/O access. Finally, we explore policies for bounding the duration of scheduling anomalies. (c) 2008 Elsevier Inc. All rights reserved.
An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache
(2018-04-01)
Ji, Cheng
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Chang, Li-Pin
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Wu, Chao
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Shi, Liang
;
Xue, Chun Jason
NAND flash memory has been the default storage component in embedded systems. One of the key technologies for flash management is the address mapping scheme between logical addresses and physical addresses, which deals with the inability of in-place-updating in flash memory. Demand-based page-level mapping cache is often applied to match the cache size constraint and performance requirement of embedded storage systems. However, recent studies showed that the management overhead of mapping cache schemes is sensitive to the host I/O patterns, especially when the mapping cache is small. This paper presents a novel I/O scheduling scheme, called MAP+, to alleviate this problem. The proposed scheduling approach reorders I/O requests for performance improvement from two angles. Prioritizing the requests that will hit in the mapping cache, and grouping requests with related logical addresses into large batches. Batches of requests are reordered to further optimize request waiting time. Experimental results show that MAP+ improved upon traditional I/O schedulers by 48% and 18% in terms of read and write latencies, respectively.
Calibrating parameters and formulas for process-level energy consumption profiling in smartphones
(2014-09-01)
Lin, Ying-Dar
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Rattagan, Ekarat
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Lai, Yuan-Cheng
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Chang, Li-Pin
;
Yo, Yun-Chien
Battery-powered mobile devices substantially constrain energy resources. Process-level energy profiling tools can identify the most energy-consuming process and detail the energy usage of hardware components. With the help of energy profiling tools, programmers can fine-tune the energy consumption of processes to extend battery lifetime. However, profiling tools are highly dependent on hardware and must be calibrated for each hardware platform. Furthermore, for any new hardware components, new energy estimation formulas must be created. To solve these two problems regarding off-the-shelf products, this work proposes a two-phase calibrating approach. The first phase reconstructs the power table with a power meter, while the second creates new energy estimation formulas using linear regression analysis. The accuracy of the calibrated tool was evaluated in five scenarios and its error ratio is proven to be below 10%, occasionally less than 5%. Hence, this proposed approach to energy consumption profiling represents a major step in off-the-shelf devices. (C) 2014 Elsevier Ltd. All rights reserved.
Configurability of performance and overheads in flash management*
(2006)
Kuo, Tei-Wei
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Hsieh, Jen-Wei
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Chang, Li-Pin
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Chang, Yuan-Hao
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資訊工程學系
Flash memory has been widely considered as a good alternative for storage system implementations because it offers superior vibration tolerance and power efficiency, compared to hard-disks. Because of its unique characteristics, direct applications of disk management methods over flash memory might result in performance degradation and even the reducing of the lifetime. The management issues become even more challenging, especially when the capacity of flash memory increases significantly in the past few years. In this paper, we summarize our work on several important issues in flash memory management, where system performance and management overheads are considered. The capability of the proposed methodology was evaluated by a series of experiments to provide more insights in system designs.
Current-Aware Flash Scheduling for Current Capping in Solid State Disks
(2020-02-01)
Chang, Li-Pin
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Cheng, Chia-Hsiang
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Chang, Shu-Ting
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Chou, Po-Han
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資訊工程學系
Solid state disks (SSDs) employ internal parallelism to boost their input/output (I/O) performance, but a high degree of flash parallelism inevitably consumes a high level of current. To budget power or support multiple power sources, system software may force an SSD into a new power mode that has a specific current supply limit. This paper introduces a firmware approach to optimize SSD internal parallelism subject to a current supply limit. The proposed method involves two steps. First, we constructed current models of flash operations on the basis of real-world measurement results. Second, we designed a firmware scheduler to determine the actual starting time of each flash operation. The proposed scheduler accounted for flash aging, process variation, and internal resource contention, and it avoided any current cap violation by checking a few time points instead of every unit of time. Our experimental results indicated that the proposed approach outperformed existing methods with respect to I/O response time and throughput under realistic workloads.
Detecting Solid-State Disk Geometry for Write Pattern Optimization
(2011-01-01)
Kuo, Chun-Chieh
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Hsieh, Jen-Wei
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Chang, Li-Pin
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交大名義發表
;
National Chiao Tung University
Solid-state disks use flash memory as their storage medium, and adopt a firmware layer that makes data mapping and wear leveling transparent to the hosts. Even though solid-state disks emulate a collection of logical sectors, the I/O delays of accessing all these logical sectors are not uniform because the management of flash memory is subject to many physical constraints of flash memory. This work proposes a collection of black-box tests can detect the geometry inside of a solid-state disk. The host system software can arrange data in the logical disk space according to the detected geometry information to match the host write pattern with the device characteristic for reducing the flash management overhead in solid-state disks.
Dual Greedy: Adaptive Garbage Collection for Page-Mapping Solid-State Disks
(2012-01-01)
Lin, Wen-Huei
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Chang, Li-Pin
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資訊工程學系
;
Department of Computer Science
In the recent years, commodity solid-state disks have started adopting powerful controllers and implemented page-level mapping for flash management. However, many of these models still use primitive garbage-collection algorithms, because prior approaches do not scale up with the dramatic increase of flash capacity. This study introduces Dual Greedy for garbage collection in page-level mapping. Dual Greedy identifies page-accurate data hotness using only block-level information, and adaptively switches its preference of victim selection between block space utilization and block stability. It can run in constant time and use very limited RAM space. Our experimental results show that Dual Greedy outperforms existing approaches in terms of garbage-collection overhead, especially with large flash blocks.
Eager Synching: A Selective Logging Strategy for Fast fsync() on Flash-Based Android Devices
(2017-04-01)
Chang, Li-Pin
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Sung, Po-Han
;
Chen, Po-Tsang
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Chen, Po-Hung
;
資訊工程學系
Flash storage has been a standard component in Android devices. Recent research has reported that application data management in Android involves frequent fsync() operations. The current fsync() implementations, including those of ext4 and F2FS, have several common drawbacks. Specifically, ext4 commits a transaction every time to sync a file, whereas F2FS commits a checkpoint to sync a directory. Committing a transaction or checkpoint flushes all dirty data from the page cache to the flash storage via many small, random block write requests. The resultant high I/O frequency and excessive write traffic cause a high fsync() latency. This study presents an efficient fsync() method, called eager synching, which is based on a simple idea: write less, and write sequentially. To sync a file, eager synching writes only a subset of all dirty data in the page cache to a sequential log space using a few sequential block write requests. It does not involve transaction or checkpoint committing. We successfully implemented eager synching in ext4 and F2FS, and our experimental results show that, compared with the original fsync() methods of ext4 and F2FS, eager synching reduced the average and maximum fsync() latencies by up to 72% and 91%, respectively, block-level write traffic by up to 35%, and I/O frequency by up to 66%. Through enhanced crash recovery procedures, eager synching can successfully recover all previously synched files while still guaranteeing the file system integrity. We also conducted live application replays using the proposed eager synching approach and observed that this approach significantly improved the application frame updating rate and application execution time.
Event-driven dynamic workload scaling for uniprocessor real-time embedded systems
(2007-09-01)
Chang, Li-Pin
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Chen, Ya-Shu
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資訊工程學系
;
Department of Computer Science
Many embedded systems are designed to take timely reactions to the occurrences of particular scenarios. Such systems could sometimes experience transient overloads because of workload bursts or hardware malfunctions. Thus a mechanism to focus limited resources on the processing of urgent events is a key to retain system validity under stressing workloads. In this paper, we propose a new approach for workload Scaling in uniprocessor real-time embedded systems. The idea is to view the system as a black box, and workload scaling for overload management can be done via very intuitive primitives, i.e., how hardware events are selectively fed into the system. Such a new approach removes the need for the adjustments of task periods and task phasing, which is important for many workload-scaling techniques. The proposed approach is implemented in a real-time surveillance system. Experimental results show that the system still delivers good accuracy and high responsiveness for visual-object tracking under the presence of overloads.
Exploiting Page Correlations for Write Buffering in Page-Mapping Multichannel SSDs
(2016)
Huang, Sheng-Min
;
Chang, Li-Pin
;
資訊工程學系
;
Department of Computer Science
Advanced solid-state disks (SSDs) have been equipped with page-mapping flash translation layers and multichannel architectures. The SSDs employ a RAM-based write buffer, which delays write requests for reducing write traffic, reorders requests for mitigating garbage-collection overhead, and produces parallel page writes for improving channel time utilization. This work presents a novel write buffer algorithm that exploits temporal and spatial correlations among buffer pages. The write-buffer groups temporally or spatially correlate buffer pages and then write the grouped buffer pages to the same flash block. In this way, when the correlated page data are updated in the future, flash blocks will receive bulk page invalidations and become good candidates for garbage collection. With multichannel architectures, the write buffer adaptively disperses read-most sequential data over channels for high page-level parallelism of sequential reads, while clustering write-most sequential data in the same channel for a reduced cost of garbage collection. We evaluated the proposed method and previously proposed buffer algorithms. Our method was shown to outperform the existing methods by up to 134%. We also implemented our buffer design on the OpenSSD platform; the time and space overheads of our design were reported to be very low.
Fast File Synching for Applications in Flash-Based Android Devices
(2014-01-01)
Chang, Li-Pin
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Sung, Po-Han
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Chen, Po-Hung
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交大名義發表
;
National Chiao Tung University
Flash-storage-based Android devices have been a very popular design option for hand-held devices. Recent research pointed out that application-level data management in Android systems involves frequent file synching operations (i.e., fsync() calls). Because fsync() is a blocking call, applications could suffer from poor response if the fsync() implementation is inefficient. The existing methods of file synching in Android systems are not flash-aware, and they could either significantly increase the block-level write randomness or excessively increase the block write traffic. This work introduces an efficient design of fsync(), called eager synching. Our basic idea is simple: write less, and write sequentially. When a file is being synched, eager synching first identifies the dirty data related to the file, and then write the dirty data to a sequential log space. This way, fsync() calls can be quickly serviced by a small amount of fast, sequential block writes on the flash storage. Our experimental results show that, under the workloads of typical Android applications, the average and max fsync() latencies were reduced by up to 72% and 91%, respectively, and the block-level write traffic was reduced by up to 35%.