Browsing by Author "Chang, Meng-Fan"

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A 0.5V 1.27mW Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia
(2014-01-01)
Tang, Kea-Tiong
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Chiu, Shih-Wen
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Shih, Chung-Hung
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Chang, Chia-Ling
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Yang, Chia-Min
A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip
(2018-10-01)
Chou, Ting-I
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Chang, Kwuang-Han
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Jhang, Jia-Yin
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Chiu, Shih-Wen
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Wang, Guoxing
Miniature gas detection system is desirable for many applications. In this brief, we propose a fully integrated nose-on-a-chip for mobile phones and wearable devices. The chip has 36 on-chip sensors, a 36-channel adaptive interface with an integrated programmable amplifier, a four-channel frequency readout interface, one on-chip temperature sensor, a successive approximation analog-to-digital converter, a scalable learning kernel cluster, and a reduced instruction set computing core with low-voltage static random-access memory. This chip is fabricated using the TSMC 180-nm CMOS process and consumes 2.6 mW at 1 V. on-chip temperature and humidity sensors are included in this system for acquiring environmental information. An environmental compensation algorithm based on common principal components analysis is also implemented for high-accuracy odor classification. This fully integrated nose-on-a-chip provides promising results for odor detection and classification for use in mobile and wearable device applications.
A 256b-Wordlength ReRAM-based TCAM with 1ns Search-Time and 14x Improvement in WordLength-EnergyEfficiency-Density Product using 2.5T1R cell
(2016)
Lin, Chien-Chen
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Hung, Jui-Yu
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Lin, Wen-Zhang
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Lo, Chieh-Pu
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Chiang, Yen-Ning
A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing
(2017-06-01)
Chang, Meng-Fan
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Lin, Chien-Chen
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Lee, Albert
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Chiang, Yen-Ning
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Kuo, Chia-Chen
Existing nonvolatile ternary content-addressable-memory (nvTCAM) suffers from limited word-length (WDL), large write-energy (E-W) and search-energy (E-S), and large cell area (A). This paper develops a 3T1R nvTCAM cell using a single multiple-level cell (MLC)-resistive RAM (ReRAM) device to achieve long WDL, lower E-W and E-S, and reduced cell area. Two peripheral control schemes were developed, dual-replica-row self-timed and invalid-entry power consumption suppression (IEPCS), for the suppression of dc current in 3T1R nvTCAM cells in order to reduce E-S. Two versions of the IEPCS scheme were developed (basic and charge-recycle-controlled) to alter the tradeoff between area overhead and power consumption in the updating of invalid-bits. A 128 b x 64 b 3T1R nvTCAM macro was fabricated using back-end-of-line ReRAM under 90-nm CMOS process. The fabricated MLC-based 3T1R nvTCAM macro achieved sub-1-ns search-delay and sub-6-ns wake-up time with supply voltage of 1 V and WDL = 64 b.
A 3T1R Nonvolatile TCAM Using MLC ReRAM with Sub-1ns Search Time
(2015-01-01)
Chang, Meng-Fan
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Lin, Chien-Chen
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Lee, Albert
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Kuo, Chia-Chen
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Yang, Geng-Hau
A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata
(2017-12-01)
Tsai, Hsiang-Jen
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Chen, Chien-Chih
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Peng, Yin-Chi
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Tsao, Ya-Han
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Chiang, Yen-Ning
Regular expression matching becomes indispensable elements of Internet of Things network security. However, traditional ternary content addressable memory (TCAM) search engine is unable to handle patterns with wildcards, as it precisely tracks only one active state with single transition. This paper proposes a promising simultaneous pattern matching methodology for wildcard patterns by two separated engines to represent discrete finite automata. A key preprocessing to encode possible postfix pattern by a unique key ensures that follow-up patterns can accurately traverse all possible matches with limited hardware resources. This approach is practical and scalable for achieving good performance and low space consumption in network security, and it can be applicable to any regular expressions even with multiwildcard patterns. The experimental results demonstrate that this scheme can efficiently and accurately recognize wildcard patterns by simultaneously tracking only two active states. By adopting SRAM TCAM in the proposed architecture, the energy consumption is reduced to around 39%, compared with the energy consumption using a computing system that contains a large memory lookup and comparison overhead.
A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia
(2014-12-01)
Chiu, Shih-Wen
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Wang, Jen-Huo
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Chang, Kwuang-Han
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Chang, Ting-Hau
;
Wang, Chia-Min
Ventilator-associated pneumonia (VAP) still lacks a rapid diagnostic strategy. This study proposes installing a nose-on-a-chip at the proximal end of an expiratory circuit of a ventilator to monitor and to detect metabolite of pneumonia in the early stage. The nose-on-a-chip was designed and fabricated in a 90-nm 1P9M CMOS technology in order to downsize the gas detection system. The chip has eight on-chip sensors, an adaptive interface, a successive approximation analog-to-digital converter (SAR ADC), a learning kernel of continuous restricted Boltzmann machine (CRBM), and a RISC-core with low-voltage SRAM. The functionality of VAP identification was verified using clinical data. In total, 76 samples infected with pneumonia (19 Klebsiella, 25 Pseudomonas aeruginosa, 16 Staphylococcus aureus, and 16 Candida) and 41 uninfected samples were collected as the experimental group and the control group, respectively. The results revealed a very high VAP identification rate at 94.06% for identifying healthy and infected patients. A 100% accuracy to identify the microorganisms of Klebsiella, Pseudomonas aeruginosa, Staphylococcus aureus, and Candida from VAP infected patients was achieved. This chip only consumes 1.27 mW at a 0.5 V supply voltage. This work provides a promising solution for the long-term unresolved rapid VAP diagnostic problem.
A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing
(2016-11)
Chang, Meng-Fan
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Huang, Lie-Yue
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Lin, Wen-Zhang
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Chiang, Yen-Ning
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Kuo, Chia-Chen
This paper outlines the RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) with the following benefits: 1) reduced NVM-stress; 2) reduced ML parasitic load; and 3) suppression of match-line (ML) leakage current from match cells. The RCSD-4T2R cell achieves a 6x reduction in NVM-stress, a 2x increase in maximum wordlength, and a 2x reduction in search delay. In this paper, we also outline two search schemes, referred to as dynamic source-line pulse controlled (DSL-PC) search and dataline-pulse controlled (DL-PC) search, which were developed specifically for the RCSD-4T2R nvTCAM. We fabricated a 128 x 32 b RCSD-4T2R nvTCAM macro with HfO ReRAM using a 180 nm CMOS process. Using the DSL-PC and DL-PC schemes, the measured search delay of the RCSD-4T2R nvTCAM macro was 1.2 ns under typical VDD.
A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage Class Memory Applications
(2017-01)
Khwa, Win-San
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Chang, Meng-Fan
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Wu, Jau-Yi
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Lee, Ming-Hsiu
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Su, Tzu-Hsiang
For multilevel cell (MLC) phase change memory (PCM), resistance drift ( R-drift) phenomenon causes cell resistance to increase with time, even at room temperature. As a result, the fixed-threshold-retention (FTR) raw-bit-error-rate (RBER) surpasses practical ECC correction ability within hours after being programmed. This study proposes a resistance drift compensation (RDC) scheme to mitigate R-drift issue. The proposed RDC scheme realizes PCM drift compensation and features RDC pulse to suppress ECC decoding failure. The proposed approach was validated using a 90-nm 128M cells PCM chip and an FPGA-based memory controller verification system. The MLC PCM FTR RBER has been suppressed by over 100x, thereby bringing it within ECC capability. The effectiveness of the RDC scheme was verified up to 106 cycles.
A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage Class Memory Applications
(2017-01)
Khwa, Win-San
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Chang, Meng-Fan
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Wu, Jau-Yi
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Lee, Ming-Hsiu
;
Su, Tzu-Hsiang
For multilevel cell (MLC) phase change memory (PCM), resistance drift ( R-drift) phenomenon causes cell resistance to increase with time, even at room temperature. As a result, the fixed-threshold-retention (FTR) raw-bit-error-rate (RBER) surpasses practical ECC correction ability within hours after being programmed. This study proposes a resistance drift compensation (RDC) scheme to mitigate R-drift issue. The proposed RDC scheme realizes PCM drift compensation and features RDC pulse to suppress ECC decoding failure. The proposed approach was validated using a 90-nm 128M cells PCM chip and an FPGA-based memory controller verification system. The MLC PCM FTR RBER has been suppressed by over 100x, thereby bringing it within ECC capability. The effectiveness of the RDC scheme was verified up to 106 cycles.
A Resistance-Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage-Class Memory Applications
(2016)
Khwa, Win-San
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Chang, Meng-Fan
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Wu, Jau-Yi
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Lee, Ming-Hsiu
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Su, Tzu-Hsiang
a-SiGeC Thin Film Photovoltaic Enabled Self-Power Monolithic 3D IC Under Indoor Illumination
(2016)
Kao, Ming-Hsuan
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Yang, Chih-Chao
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Wu, Tsung-Ta
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Hsieh, Tung-Ying
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Huang, Wen-Hsieh
Low temperature a-SiGeC thin film photovoltaic (TFPV) ambient light-energy harvesters monolithically integrated with high performance 3D sequentially stackable device were demonstrated in this article. The 3D stackable device with threshold voltage engineering and driving current boosting technologies enable excellent current controllability to achieve low I-off and high I-on operation condition for integrated circuit design. The monolithically stacking of Si thin-film energy harvester, which provide output power (21.93uW/cm(2)) under 450 lux indoor illumination, envisions self-power and low cost 3D(+)IC for internet of things.
Design of a 0.5V 1.68mW Nose-on-a-Chip for Rapid Screen of Chronic Obstructive Pulmonary Disease
(2016-01-01)
Chou, Ting-I
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Chiu, Shih-Wen
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Chang, Kwuang-Han
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Chen, Yi-Ju
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Tang, Chen-Ting
Chronic obstructive pulmonary disease (COPD) still lacks a rapid diagnosis strategy. In this paper, we propose a low-power nose-on-a-chip for rapid COPD screening. This chip is designed for implementation in a personal handheld device that detects patient breath for COPD diagnosis. The chip has 36 on-chip sensors, a 36-channel adaptive interface with an integrated programmable amplifier, a four-channel frequency readout interface, one on-chip temperature sensor, a two-channel successive approximation analog-to-digital converter, a scalable learning kernel cluster, and a reduced instruction set computing core with low-voltage static random-access memory. This chip is fabricated in 90 nm CMOS and consumes 1.68 mW at 0.5 V. In simulation, the system distinguished between undiseased and diseased patients with 90.82% accuracy for a set of diseases including COPD and asthma and exhibited 92.31% accuracy for identifying patients with COPD or asthma. The system classified severity levels of COPD under four labels (normal, mild, moderate, and severe) with 92.00% accuracy. Accordingly, this work provides a promising solution for the unmet medical need of rapid COPD screening.
Energy-Efficient Non-Volatile TCAM Search Engine Design Using Priority-Decision in Memory Technology for DPI
(2015)
Tsai, Hsiang-Jen
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Yang, Keng-Hao
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Peng, Yin-Chi
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Lin, Chien-Chen
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Tsao, Ya-Han
TCAM-based search engines are widely used in regular expression matching across multiple packets. However, the use of priority encoder results in increased energy consumption of pattern updates and search operations. This work, proposes a promising memory technology, called Priority-Decision in Memory (PDM), which eliminates the need for priority encoders and removes restrictions on ordering, meaning that patterns can be stored in an arbitrary order without sorting their lengths. Moreover, we present a Sequential Input-State Search (SIS) scheme to disable the mass of redundant search operations in state segments, based on the analysis distribution of hex signatures in a virus database. Experimental results demonstrate that PDM-based technology can improve update energy consumption of nvTCAM search engines by 36%similar to 67% because most of the energy in the latter is used to reorder. By adopting the SIS-based method to avoid unnecessarily search operations in a TCAM array, the search energy reduction is around 64% of nvTCAM search engines.
eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache
(2017-04-01)
Yang, Keng-Hao
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Tsai, Hsiang-Jen
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Li, Chia-Yin
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Jendra, Paul
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Chang, Meng-Fan
As 2.5D/3D die stacking technology emerges, stacked dynamic random access memory (DRAM) has been proposed as a cache due to its large capacity in order to bridge the latency gap between off-chip memory and SRAM caches. The main problems in utilizing a DRAM cache are the high tag storage overhead and the high lookup latency. To address these, we propose tags-in-eDRAM (embedded DRAM) due to its higher density and lower latency. This paper presents an eTag DRAM cache architecture that is composed of a novel tag-comparison-inmemory scheme to achieve direct data access. It eliminates access latency and comparison power by pushing tag-comparison into the sense amplifier. Furthermore, we propose a Merged Tag to enhance the eTag DRAM cache by comparing last-level cache tags and DRAM cache tags in parallel. Simulation results show that the eTag DRAM cache improves energy efficiency by 15.4% and 33.9% in 4-core and 8-core workloads, respectively. Additionally, the Merged Tag achieves 32.1% and 48.7% energy efficiency improvements in 4-core and 8-core workloads, respectively.
Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester
(2014)
Shen, Chang-Hong
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Wu, Tsung-Ta
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Chen, Chien-Fu
For the first time, we report heterogeneously integrated sub-40nm epi-like Ge/Si monolithic 3D-IC with low-power logic/NVM circuits and efficient photovoltaic energy harvester. Threshold voltage engineering and driving current boosting technologies enable stackable Ge/Si UTB (< 15nm) MOSFETs, CMOS inverter and SRAM (SNM=270mV@0.7V) achieve low operation voltage. Stackable 1-T NVM with high speed (100ns) and low driving-voltage operation provide power-off storage while SRAM serve as power-on working memory. 100% aperture ratio SiGeC ambient light energy harvester with maximum output power of 7mW/cm(2) layered on the monolithic 3D-IC chip envisions a self-powered monolithic 3D-IC technology for advanced low-power wire-less sensor networks, wearable devices, and devices for Internet of Things.
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC)
(2020-01-01)
Carusone, Tony Chan
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Seok, Mingoo
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Chang, Hsie-Chia
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Chang, Meng-Fan
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電子工程學系及電子研究所
Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination
(2014-01-01)
Tsai, Hsiang-Jen
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Chen, Chien-Chih
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Yang, Keng-Hao
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Yang, Ting-Chin
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Huang, Li-Yue
NVM has commonly been used to address increasingly large last-level caches (LLCs) requirements by reducing leakage. However, frequent data-writing operations result in increased energy consumption. In this context, a promising memory technology, Non-volatile SRAM (nvSRAM), enables normal and standby operation modes which can be used to store various types of data. However, nvSRAM suffers from high dynamic energy usage due to frequent switching between operation modes. In this paper, we propose a redundant store elimination (RSE) scheme which, on average, discards 94% of needless bit-write operations. Moreover, we present a retention-aware cache management policy to reduce data updates of cache blocks, based on the correlation between data lifetime and cache types. Experimental results demonstrate that our proposal can improve energy consumption of SRAM-based and RRAM-based LLCs by 57% and 31%, respectively.
Logic/Memory Hybrid 3D Sequentially Integrated Circuit Using Low Thermal Budget Laser Process
(2015)
Yang, Chih-Chao
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Hsieh, Tung-Ying
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Huang, Wen-Hsien
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Wu, Tsung-Ta
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Wang, Hsing-Hsiang
High performance 3D sequentially stackable nanowire FETs and non-volatile memories (NVMs) with threshold voltage engineering and driving current boosting technologies were demonstrated by using low thermal budget nanosecond laser crystallization and laser activation technologies. The local heating laser process without damaging the underlying device/circuit realizes the across -layer and in -layer integration of high-speed 3ps logic circuits and 1-T 100ns plasma-MONOS NVMs as well as low driving-voltage 6T SRAMs with static noise margin (SNM) of 280 mV. Such logic/memory hybrid 3D sequentially integrated circuit provides power efficient computing and storage. Moreover, the monolithically stacking of Si thin-film energy harvester envisions lower power and low cost 3D(+)IC for internet of things.
Method for eliminating crosstalk in a metal programmable read only memory
(2006-07-06)
Chang, Meng-Fan
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Wen, Kuei-Ann
The present invention provides a method for eliminating crosstalk (coupling noise) in a metal programmable read only memory. The metal programmable read only memory comprises a plurality of bit lines, a plurality of word lines, a plurality of precharge transistors, and a plurality of clamp transistors. When one of the bit lines is selected, bit lines adjacent to the selected bit line are fixed to a voltage value (VDD, GND or other voltages) by the clamp transistors. The clamping method can not cause voltage drops to the adjacent bit lines, and the crosstalk on the selected bit line can be eliminated simultaneously, so that the problem of read failures caused by the crosstalk in the high-speed metal programmable read only memory can be solved, and a higher speed can be reached.