Browsing by Author "Chang, Ming-Hung"

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A 1.9mW portable ADPLL-based frequency synthesizer for high speed clock generation
(2007)
Chang, Ming-Hung
;
Yang, Zong-Xi
;
Hwang, Wei
;
電子與資訊研究中心
;
Microelectronics and Information Systems Research Center
An ADPLL-based frequency synthesizer has been designed and implemented with TSMC 130nm technology model. The cores of it are digital controlled oscillator (DCO) and phase frequency detector (PFD). A modified digitally controlled delay element (DCDE) with characteristics of its monotonicity and insensitivity to PVT variations is presented for the DCO design. A new PFD architecture that can finish phase and frequency comparison and adjustment in one reference cycle is presented. This frequency synthesizer can operate from 300MHz to 1GHz, and achieve frequency acquisition in fifteen reference clock cycles (worst case scenario). The peak-to-peak jitter of the output clock is less than 120ps at 300MRz. Furthermore, the design has been ported to TSMC 100nm process as a reusable IP block verification. The total power dissipation of the ADPLL-based frequency synthesizer is 1.9mW (TSMC 100nm technology) at 1GHz with a 1.2V power supply. With such specifications, it is suitable for high speed clock generation in system-on-a-chip (SoC) applications.
A 2.1-mu W 0.3V-1.0V Wide Locking Range Multiphase DLL Using Self-Estimated SAR Algorithm
(2009)
Chang, Yi-Ming
;
Chang, Ming-Hung
;
Hwang, Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an all-digital multiphase delay-locked loop (ADMDLL) for wide-locking range and micro-power applications. To enhance locking range of the ADMDLL, we proposed the self-estimated successive approximation register-controlled (SESAR) algorithm, which uses the frequency-estimation selector (FES) to avoid harmonic lock issue. In addition, the FES can reuse the delay line to reduce circuit area and power dissipation significantly. By using the stack effect, the proposed leakage-reduced delay unit can save 12% leakage power consumption. After locking, the dynamic frequency monitor window is proposed to compensation phase error caused by PVT variations. The proposed ADMDLL is capable of operating in wide supply voltage range from 0.3V to 1.0V. The power dissipation is only 520 mu W at 1.25GHz/1.0V, and 2.1 mu W at 13MHz/0.3V, respectively. This work is based on UMC 90nm standard CMOS technology.
A 300-mV 36-mu W Multiphase Dual Digital Clock Output Generator with Self-Calibration
(2008)
Chang, Ming-Hung
;
Chuang, Li-Pu
;
Chang, I-Ming
;
Hwang, Wei
;
電子工程學系及電子研究所
A 300mV 20MHz-35OMHz low variation all-digital multiphase dual clock output generator with rapid self-calibration has been designed with UMC 90nm CMOS technology model. The PVT immunity properties of several classic delay elements in low voltage era have been studied. A low voltage calibration unit is also proposed to reduce the maximum multiphase error no larger than 120ps when delay-locked loop is operating at 40MHz/300mV. A novel static current-mirror-based phase blender is developed to provide wide range accurate twice multiphase information, and phase error is reduced by no more than 11.83%. The clock generator could provide more independent outputs by simply using additional edge combiner. The frequency and phase of output clock could be dynamically adjusted without relocking process. The total power dissipation of the all-digital multiphase dual digital clock output generator is 36 mu W at 40MHz/300mV.
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop
(2008)
Chuang, Li-Pu
;
Chang, Ming-Hung
;
Huang, Po-Tsang
;
Kan, Chih-Hao
;
Hwang, Wei
A 333MHz-1GHz all-digital multiphase delay-locked loop with precise multi-phase output has been designed with TSMC 130nm CMOS technology model. A modified binary search algorithm is proposed to match up a linear approximate delay element (LADE). The LADE property of linearity and insensitive to PVT variations is good for digitally-controlled delay element. The lock-in time could be reduced down to 14 reference clock cycles, and enhance the operation range based on LADE[binary search algorithm co-operate effort. The timing error caused by process mismatch is further reduced by proposed rapid self-calibration (RSC) algorithm. A calibration unit is designed based on RSC algorithm, which reduces the maximum timing error to less than 9ps when DLL is operating at 500MHz. The entire calibration unit could be turned off after calibration procedure is complete to reduce power consumption. The total power dissipation of the all-digital self-calibrated multiphase delay-locked loop is 5.2mW at 1GHz with a 1.2V power supply.
A controllable low-power dual-port embedded SRAM for DSP processor
(2008)
Yang, Hao-I
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Chang, Ming-Hung
;
Lin, Tay-Jyi
;
Ou, Shih-Hao
;
Deng, Siang-Sen
In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A codesign of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable precharged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.
A DUAL-EDGED TRIGGERED EXPLICIT-PULSED LEVEL CONVERTING FLIP-FLOP WITH A WIDE OPERATION RANGE
(2013-01-01)
Chen, Mei-Wei
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Chang, Ming-Hung
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Wu, Pei-Chen
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Kuo, Yi-Ping
;
Yang, Chun-Lin
In a multiple supply voltage system, the level converters are inserted between two different voltage domains. However, those level converters may cause the propagation delays and power consumption. In order to eliminate the overhead of level conversion, a dual-edged triggered explicitpulsed level converting flip-flop (DETEP-LCFF) with a wide operation range is proposed. It is composed of a clock pulse generator and a modified differential cascode voltage switch with pass gate (DCVSPG) latch. The clock pulse generator has the symmetric pulse triggering time and holding period helping shorten the D-Q delay. By employed diode-connected PMOS transistors and two NMOS transistor stacked below the diode PMOS transistors, the proposed DETEP-LCFF can be operated from near-threshold region to superthreshold region. It is implemented in TSMC 65nm CMOS technology. It functions correctly across all process corners with a wide input voltage range, from 400mV to 1V. The proposed LCFF has a minimum D-Q delay of 781 ps, a setup time of 610ps, and a power dissipation of 2.3 mu W when the input voltage is OAV.
A flexible two-layer external memory management for H.264/AVC decoder
(2007)
Chang, Chang-Hsuan
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Chang, Ming-Hung
;
Hwang, Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a flexible two-layer external memory management for H.264/AVC decoder is proposed. Power consumption and data access latency caused by being fetched to/from the off-chip memory greatly affect multimedia system performance. The proposed memory controller consists of two layers. The first layer is the address translation which provides an efficient pixel data arrangement to reduce the row-miss occurrence. The second layer is the external memory interface (EMI) which can further reduce access latency up to 70% by using the specific command FIFO and a unified FSM with generic scheduling. Particularly, the memory utilization can be increased about 3 times as compared with traditional method after combining the address translation layer with external memory interface. Similarly, the proposed memory controller unit is feasible and beneficial for future memory-bandwidth-constraint System-on-Chip applications.
A low-power low-swing single-ended multi-port SRAM
(2007)
Yang, Hao-, I
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Chang, Ming-Hung
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Lai, Ssu-Yun
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Wang, Hsiang-Fei
;
Hwang, Wei
In this paper, a new single-ended 6-T SRAM cell is proposed. It has a very strong static noise margin (SNM) during read cycles. Meanwhile, data can be easily written because of floating virtual ground and I-T equalizer insertion within cell. Low-swing writing ability is achieved by these two approaches. A single-ended current-mode sensing amplifier is also presented. This amplifier can sense a very small swing of bitline, equipping with a high noise-rejection and high PVT-tolerance ability. A low-swing 3-port 64x32-bit SRAM macro is simulated in TSMC 130nm CMOS technology. It consumes a minimum of 725 mu W and 658 mu W per-port at IGHz with 1.2V supply voltage for read and write power, respectively.
An Energy-Efficient 10T SRAM-based FIFO Memory Operating in Near-/Sub-threshold Regions
(2011)
Du, Wei-Hung
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Chang, Ming-Hung
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Yang, Hao-Yi
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Hwang, Wei
;
電子工程學系及電子研究所
In this paper, an ultra-low power (ULP) 16Kb SRAM-based first-in first-out (FIFO) memory is proposed for wireless body area networks (WBANs). The proposed FIFO memory is capable of operating in ultra-low voltage (ULV) regime with high variation immunity. An ULP near-/subthreshold 10 transistors (10T) SRAM bit-cell is proposed to be the storage element for improving write variation in ULV regime and eliminate the data-dependent bit-line leakage. The proposed SRAM-based FIFO memory also features adaptive power control circuit, counter-based pointers, and a smart replica read/write control unit. The proposed FIFO is implemented to achieve a minimum operating voltage of 400mV in UMC 90nm CMOS technology. The write power is 2.09 mu W at 50kHz and the read power is 2.25 mu W at 625kHz.
Design and Iso-Area V-min Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS
(2012-07-01)
Chang, Ming-Hung
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Chiu, Yi-Te
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Hwang, Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
"In this brief, a 9T bit cell is proposed to enhance write ability by cutting off the positive feedback loop of a static random-access memory (SRAM) cross-coupled inverter pair. In read mode, an access buffer is designed to isolate the storage node from the read path for better read robustness and leakage reduction. The bit-interleaving scheme is allowed by incorporating the proposed 9T SRAM bit cell with additional write wordlines (WWL/WWLb) for soft-error tolerance. A 1-kb 9T 4-to-1 bit-interleaved SRAM is implemented in 65-nm bulk CMOS technology. The experimental results demonstrate that the test chip minimum energy point occurs at 0.3-V supply voltage. It can achieve an operation frequency of 909 kHz with 3.51-mu W active power consumption."
Fully On-Chip Temperature, Process, and Voltage Sensors
(2010)
Chen, Shi-Wen
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Chang, Ming-Hung
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Hsieh, Wei-Chih
;
Hwang, Wei
;
電子與資訊研究中心
A process, voltage, and temperature (PVT) sensor without a voltage/current analog-to-digital converter (ADC) or bandgap reference is proposed for high accuracy, low power, and wide voltage range portable applications. Conventional temperature sensors rely on voltage/current ADC for digital output code conversion. The proposed temperature sensor generates a clock frequency proportional to the measured temperature, and converts the frequency into a corresponding digital code. The generated digital code is still under the influence of PVT variations. Two distinct sensors for voltage and process monitoring are also proposed to enhance temperature sensor environmental variation immunity. The property of zero temperature coefficient (ZTC) bias point is used to remove temperature effect. The proposed wide voltage range low power PVT sensor is designed in UMC 65nm bulk CMOS technology. It is capable of operating over a wide voltage range within 0.3V similar to V. The power consumption is no more than 3.7 mu W at 0.3V supply voltage and a high sample rate of 10k samples/sec. The temperature error is merely -0.8 similar to 0.8 degrees C.
High Efficiency Power Management System for Solar Energy Harvesting Applications
(2010)
Chang, Ming-Hung
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Wu, Jung-Yi
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Hsieh, Wei-Chih
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Lin, Shang-Yuan
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Liang, You-Wei
A high efficiency power management system for solar energy harvesting applications is proposed. The power management system receives power from photovoltaic (PV) cell and generate different voltage levels, they are 1V similar to 0.3V for analog circuitry and low power digital circuitry, -1.2V for super-cutoff technique in memory circuitry, and 10V for FLASH memory or I/O components. The great voltage varieties are suitable for green integrated regulator SoC electronics. The power management system also contains a rechargeable battery which is charged by multi-phase maximum power tracking (MPT) circuitry with the PV cell module. With the MPT circuitry, the power of PV cell can be regulated in the maximum power region. The average power efficiency of the MPT circuitry is up to 80%similar to 73%. All resultsare simulated in UMC 90nm bulk CMOS technology model.
Logical Effort Models with Voltage and Temperature Extensions in Super-/Near-/Sub-threshold Regions
(2011)
Chang, Ming-Hung
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Hsieh, Chung-Ying
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Chen, Mei-Wei
;
Hwang, Wei
;
電子工程學系及電子研究所
The voltage-/temperature-induced delay estimation error of conventional logical effort is much more severe in near/sub-threshold region. In this paper, super-/near-/sub-threshold logical effort models are proposed to eliminate delay estimation error caused by voltage and temperature variations. These models establish over the four different nanoscale CMOS generations. They also take environmental parameter variations with wide supply voltage 0.1 similar to 1V and full temperature -50 similar to 125 degrees C range into account. The simulation results are using UMC 90-nm, PTM 65-, 45-and 32-nm bulk CMOS technologies, respectively. The average absolute error among the three regions are only 6.01%, 4.12%, 8.01% and 6.55% for UMC 90-nm, PTM 65-, 45-and 32-nm technology, respectively. Proposed models extend the original high performance circuits design in super-threshold region to low power circuit design in near-threshold and sub-threshold regions. They are useful for future green electronics applications.
Multi-Layer Adaptive Power Management Architecture for TSV 3DIC Applications
(2013)
Chang, Ming-Hung
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Hsieh, Wei-Chih
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Wu, Pei-Chen
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Chuang, Ching-Te
;
Chen, Kuan-Neng
In this work, a multi-layer hierarchical distributed power delivery architecture for TSV 3DIC is proposed. By decoupling global and local power networks, the proposed power delivery architecture can be flexibly configured for different power requests. The decoupled power architectures can also greatly reduce the required decoupling capacitor sizes for voltage stabilization. Meanwhile, a multi-threshold CMOS switched capacitor DC-DC converter with up to 78% power efficiency is implemented in 65nm CMOS for hierarchical distributed power delivery architecture. An adaptive power management technique is presented to work in the local power network to increase the power efficiency. The proposed multi-layer hierarchical distributed power delivery architecture is also very useful for the heterogeneous integration in 3DIC chips.
Near-/Sub-V-th Process, Voltage, and Temperature (PVT) Sensors with Dynamic Voltage Selection
(2013)
Chang, Ming-Hung
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Lin, Shang-Yuan
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Wu, Pei-Chen
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Zakoretska, Olesya
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Chuang, Ching-Te
A process, voltage and temperature (PVT) sensors with dynamic voltage selection are proposed for environmental management in the ultra-low voltage dynamic voltage and frequency scaling (DVFS) system. The process and voltage (PV) sensors initially monitor the process variation. With known process information, PV sensors can real-time provide voltage variation status. The temperature sensor has six temperature sensitive ring oscillators (TSROs) generating frequency proportional to temperature. It dynamically selects the proper TSRO to convert the frequency into digital readings according to voltage status provided by PV sensors. With known process and voltage information from PV sensors, a pure temperature measurement result can be obtained. The proposed PVT sensors are designed in TSMC 65nm CMOS technology. This work can be dynamically operated over an ultra-low voltage range from 0.25V to 0.5V. Only 2.3 mu W is consumed at 0.25V. They can achieve 0.15 degrees C resolution and 50k samples/sec conversion rate.
Power gating technique for embedded pseudo SRAM
(2007)
Cheng, Ching-Yun
;
Chang, Ming-Hung
;
Hwang, Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we deploy power gating technique on a lowpower Pseudo SRAM circuit with 3TID gain cell. A 256word x 32-BL-pair 3TID gain cell array is implemented in standard logic technology with TSMC 0. l3urn model f6r multi-bank Pseudo SRAM. Each Pseudo SRAM has its independent access control unit, enabling parallel refresh and read-write accesses to different bank. By employing power gating technique in sense amplifier of 3TID gain cell array, 15% standby leakage current during sleep mode could be reduced. Also, 12% sensing speed could be enhanced when Pseudo SRAM is operated in normal mode (simulated with TSMC I 00nm technology model).
STORED DON'T-CARE BASED HIERARCHICAL SEARCH-LINE SCHEME
(2008-07-24)
CHANG, Shu-Wei
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Hwang, Wei
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Chang, Ming-Hung
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Huang, Po-Tsang
In the proposed stored don't-care hierarchical search-line scheme, a content-addressable memory (CAM) is divided into several blocks. Each block contains a plurality of local search-lines, a global search-line, a buffer and a memory cell. Data are stored in the blocks in order according to the length of the prefix. Data with the longest prefix is stored at the bottommost, and its don't-care state is used as the control signal of the buffer to control whether to transfer the data on the global search-line to the local search-line or not. The local search-line then transfer the value into the memory cell. There is no complex control circuit and extra storage device needed. Moreover, because the control signal directly comes from the don't-care state, power consumption on search-lines can be effectively reduced with no increase of search delay.