Browsing by Author "Chang, Mu-Tien"

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A 65nm low power 2T1D embedded DRAM with leakage current reduction
(2007)
Chang, Mu-Tien
;
Huang, Po-Tsang
;
Hwang, Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Gain cell memories feature high speed, low power, and high density, which are suitable for SoC designs. In this paper, low power techniques to reduce leakage currents for 2T1D gain cell memory array are presented. For each memory cell, p-type gated diode storage device is applied. In addition, footer power gating and foot driver are applied on each memory word. Simulation results show that the proposed 2T1D memory array structure has 97.7% and 80% standby power reduction over typical 2T1D and typical 3T1D memory array, respectively. All the simulation results are based on Predictive Technology Model (PTM) 65nm CMOS bulk technology.
A Fully-Differential Subthreshold SRAM Cell with Auto-Compensation
(2008)
Chang, Mu-Tien
;
Hwang, Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
SRAM cell stability is a major challenge in subthreshold SRAM design. In this paper, a robust, fully-differential subthreshold 10-transistors SRAM cell with auto-compensation is proposed. With the auto-compensation mechanism, the proposed cell exhibits better hold static noise margin (SNM). The cell structure also prevents storage nodes from bitline noise interference, thus improving read SNM. Moreover, better write ability is achieved by applying write assist technique. Based on UMC 90nm CMOS technology, simulation results shows that at 200mV supply voltage, the proposed cell has 1.22X hold SNM improvement, 2.09X read SNM improvement, and 2.03X write margin improvement compared to the conventional 6T SRAM cell.
A ROBUST ULTRA-LOW POWER ASYNCHRONOUS FIFO MEMORY WITH SELF-ADAPTIVE POWER CONTROL
(2008)
Chang, Mu-Tien
;
Huang, Po-Tsang
;
Hwang, Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With self-adaptive power control and complementary power gating techniques, leakage power of the FIFO memory array is minimized. Moreover, with the proposed dual-V(T) 7T SRAM cell, the FIFO memory has improved stability under ultra-low voltage supply. Simulation results show that the proposed scheme has 16% to 94% power reduction over conventional designs. The proposed scheme is implemented in UMC 90nm CMOS technology under 0.5V supply voltage, with 1.39uW power consumption at 5MHz reading frequency and 200kHz writing frequency.
Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus
(2010-07-08)
Chang, Mu-Tien
;
Huang, Po-Tsang
;
Hwang, Wei
The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for storing data. The access transistor is coupled to the first inverter and the second inverter, wherein the first operating elements and the second operating elements are high threshold voltage operating elements and the access transistor is low threshold voltage operating transistor. The read buffer is used for performing a read operation.