Browsing by Author "Chang, Nelson Yen-Chung"

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Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight
(2010-06-01)
Chang, Nelson Yen-Chung
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Tsai, Tsung-Hsien
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Hsu, Bo-Hsiung
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Chen, Yi-Chun
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Chang, Tian-Sheuan
High-performance real-time stereo vision system is crucial to various stereo vision applications, such as robotics, autonomous vehicles, multiview video coding, freeview TV, and 3-D video conferencing. In this paper, we proposed a high-performance hardware-friendly disparity estimation algorithm called mini-census adaptive support weight (MCADSW) and also proposed its corresponding real-time very large scale integration (VLSI) architecture. To make the proposed MCADSW algorithm hardware-friendly, we proposed simplification techniques such as using mini-census, removing proximity weight, using YUV color representation, using Manhattan color distance, and using scaled-and-truncate weight approximation. After applied these simplifications, the MCADSW algorithm was not only hardware-friendly, but was also 1.63 times faster. In the corresponding realtime VLSI architecture, we proposed partial column reuse and access reduction with expanded window to significantly reduce the bandwidth requirement. The proposed architecture was implemented using United Microelectronics Corporation (UMC) 90 nm complementary metal-oxide-semiconductor technology and can achieve a disparity estimation frame rate of 42 frames/s for common intermediate format size images when clocked at 95 MHz. The synthesized gate-count and memory size is 563k and 21.3 kB, respectively.
Analysis of Color Space and Similarity Measure Impact on Stereo Block Matching
(2008)
Chang, Nelson Yen-Chung
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Tseng, Yu-Cheng
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Chang, Tian Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The impact of color space and similarity measure on complexity, speed, and performance of stereo matching is especially important to applications adopting stereo vision. This work analyzed the complexity of several most commonly considered color space and similarity measure. In addition, the execution speed and performance of color space and similarity measure combination arc also compared on the same basis. The comparison result suggests that the Y-only rank provides the best combination under speed and performance trade-off.
Architecture design of shape-adaptive discrete cosine transform and its inverse for MPEG-4 video coding
(2008-03-01)
Hsu, Hui-Cheng
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Lee, Kun-Bin
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Chang, Nelson Yen-Chung
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Chang, Tian-Sheuan
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交大名義發表
This paper presents efficient VLSI architectures of the shape-adaptive discrete cosine transform (SA-DCT) and its inverse transform (SA-IDCT) for MPEG-4. Two of the challenges encountered during the exploitation of more efficient architectures for the SA-DCT and SA-IDCT are addressed. One challenge is to handle the architectural irregularity due to the shape-adaptive nature. The other one is to provide acceptable throughput using minimal hardware. In the algorithm-level optimization, this work exploits the numerical properties found in the transform matrices of various lengths, and derives a fine-grained zero-skipping scheme for the IDCT which can perform 22.6% more zero-skipping than the common vector-based coarse-grained zero-skipping scheme does. In the architecture-level design, the 1-D variable-length DCT/IDCT architectures designed on the basis of the numerical properties are proposed. An auto-aligned transpose memory that aligns the data of different lengths is also incorporated. In addition, a zero-index table is also included in the transpose memory to support the fine-grained zero-skipping in the SA-IDCT. The synthesized designs of the SA-DCT and SA-IDCT are implemented using UMC 0.18-mu m technology. The SA-DCT architecture has 26 635 gates, and its average cycle-throughput is 0.66 pixels/cycle, which is comparable to other proposed architectures. On the other hand, the SA-IDCT architecture has 29960 gates, and its cycle-throughput is 6.42 pixels/cycle. While decoding for CIF@30FPS, the SA-IDCT is clocked at 0.7 MHz, and the power consumption is 0.14 mW. Both the throughput and power consumption of the proposed SA-IDCT architecture are an order better than those of the existing SA-IDCT architectures.
Block-based Belief Propagation With In-place Message Updating for Stereo Vision
(2008)
Tseng, Yu-Cheng
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Chang, Nelson Yen-Chung
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The large message-memory size has been a major design issue in belief propagation for stereo matching methods. To reduce its size, we proposed an in-place message updating approach which stores new messages into expired ones. Thus, this approach only needs one message memory and a small temporary message memory. Further combining with block based belief propagation, the final architecture only needs 172KB memory and can reduce internal memory size by 40% when compared with traditional ping-pong buffer approach.
Combined frame memory motion compensation for video coding
(2006-10-01)
Chang, Nelson Yen-Chung
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The frame memory has long been the dominant component in a video decoder in terms of energy, area, and latency. We proposed a non-combined frame memory motion compensation (CFMMC) for video decoding which facilitates the characteristic of the perfect-matched macroblock (MB) to avoid unnecessary memory access and to save energy. The statistic result confirms that some sequences have more than 70% of MBs being perfect-matched MB. The CFMMC hardware architecture is further evaluated for latency, area, and energy. The hardware architecture shows that with SRAM-base frame memory, the equivalent gate count can be reduced by 37.7%, and the energy consumption and the latency may also be improved for sequences with enough percentage of perfect-matched MBs. Since the benefit of the CFMMC is highly dependent on the percentage of perfect-matched MBs, it is best suited for applications with large portion of static background, such as video surveillance, video telephony, and video conferencing.
Context-aware frame memory scheme for motion compensation in video decoding
(2007-04-26)
Chang, Nelson Yen-Chung
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Chang, Tian-Sheuan
The present invention provides a context-aware frame memory scheme for motion compensation in video decoding, which utilizes a motion compensator to receive a data block from input video decoding, follow by processing both inputted context characteristic of residual block and motion vector respectively. The conception of technology is first based on the context characteristic of input video data decoding block, if there is no residual value and motion vector, it will be defined as “perfect match block”; otherwise, “non-perfect match block” instead. Then, the circuit architecture for memory accessing in video decoding provided by present invention will perform different memory access steps for the above mentioned two types of block. If one determines that a block is “non-perfect match block”, selectively choose the reference frame as a back-up data; On contrary, if a block is “perfect match block”, it represents there is no difference between both reference frame and reconstructive frame, hence no access is required to the main frame memory, which means that the access frequency can be minimized; therefore, it can minimize the consumption of the memory capacity as well.
Data reuse analysis of local stereo matching
(2008)
Tsai, Tsung-Hsien
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Chang, Nelson Yen-Chung
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
External memory bandwidth and internal memory size have been major bottlenecks in designing VLSI architecture for real-time stereo matching hardware because of large amount of pixel data and disparity range. To address these bottlenecks, this work explores the impact of data reuse on disparity-order and pixel-order along with the partial column reuse (PCR) and vertically expanded row reuse (VERR) techniques we proposed. The analysis suggest that a disparity-order reuse with both PCR and VERR techniques is suitable for low memory cost and low external bandwidth design, whereas the pixel-order reuse with both techniques is more suitable for low computation resource requirement.
Fast SIFT Design for Real-Time Visual Feature Extraction
(2013-08-01)
Chiu, Liang-Chi
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Chang, Tian-Sheuan
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Chen, Jiun-Yen
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Chang, Nelson Yen-Chung
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電子工程學系及電子研究所
Visual feature extraction with scale invariant feature transform (SIFT) is widely used for object recognition. However, its real-time implementation suffers from long latency, heavy computation, and high memory storage because of its frame level computation with iterated Gaussian blur operations. Thus, this paper proposes a layer parallel SIFT (LPSIFT) with integral image, and its parallel hardware design with an on-the-fly feature extraction flow for real-time application needs. Compared with the original SIFT algorithm, the proposed approach reduces the computational amount by 90% and memory usage by 95%. The final implementation uses 580-K gate count with 90-nm CMOS technology, and offers 6000 feature points/frame for VGA images at 30 frames/s and similar to 2000 feature points/frame for 1920x1080 images at 30 frames/s at the clock rate of 100 MHz.
ISID : In-order scan and indexed diffusion segmentation algorithm for stereo vision
(2008)
Chan, Jing-Chu
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Chang, Nelson Yen-Chung
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Existing segmentation algorithms have irregular computing order, expensive sorting, or inefficient backtracking procedure which would reduce their processing speed. In this paper, an in-order scan and indexed diffusion (ISID) segmentation algorithm for stereo vision which is more regular and does not need sorting nor backtracking is proposed. The in-order scan plateau detection is the first step in ISID which detects whether pixels in a 3x3 sliding window belongs to the same region or not. Then the indexed upward diffusion assigns a label to an undetermined pixel using a label diffusion method. Simulation results show that with the introduced regularity and lower complexity, the proposed ISID algorithm reduces 54% and 36% of the execution time when compared with the immersion-based and toboggan-based watershed algorithm in average.
Low-Memory Cost Belief Propagation Architecture for Disparity Estimation
(2009)
Tseng, Yu-Cheng
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Chang, Nelson Yen-Chung
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In disparity estimation, belief propagation can deliver better disparity quality than other algorithms but suffer from large storage cost, especially at the message update processing. To reduce the storage cost, this paper proposes low-memory cost architectures for the message update PE to satisfy the real-time application. We propose four architectures which are post-normalization, shadow buffer, no memory, and no memory+double PE architectures. Compared to the previous design, the proposed no memory+double PE architecture can save 28% of the hardware cost at most for 320x240@30fps and 64 disparity levels.