Browsing by Author "Chang, Nien-Shyang"

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3D Heterogeneous Integration Structure Based on 40 nm- and 0.18 mu m- Technology Nodes
(2015)
Hu, Yu-Chen
;
Lin, Chun-Pin
;
Hsieh, Yu-Sheng
;
Chang, Nien-Shyang
;
Gallegos, Anthony J.
In this paper, a simple process for high yield CMOS-compatible and heterogeneous integrated chip-to-chip structure without TSV is demonstrated. This scheme provides two chips consisted of the shortest interconnect path by Cu/Sn pillar bump and electroless nickel immersion gold (ENIG) pad bonding. One of the key technologies of 3D integration process is bump plating on the uneven topography. Since passivation layer covers the periphery of the top metal layer, subsequent electroplating process resulted to the increase in height of bump edge which is higher than bump center resulting in concave shape. A new and unique plating solution was developed to solve the issue during the electroplating pillar bump. Basic electrical characteristics including resistance and current leakage were investigated with reliability tests. The stable reliability tests results and excellent electrical performance show that the 3D heterogeneous integration structure is potentially applicable for 3D applications in the future.
A Novel Flexible 3-D Heterogeneous Integration Scheme Using Electroless Plating on Chips With Advanced Technology Node
(2015-12-01)
Hu, Yu-Chen
;
Lin, Chun-Pin
;
Chang, Yao-Jen
;
Chang, Nien-Shyang
;
Sheu, Ming-Hwa
A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node.