Browsing by Author "Chang, Pin-Hsin"

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Impact of Inner Pickup on ESD Robustness of Multifinger MOSFET in 28-nm High-k/Metal Gate CMOS Process
(2015-12-01)
Lin, Chun-Yu
;
Chang, Pin-Hsin
;
Chang, Rong-Kun
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The impact of pickup structure on electrostatic discharge (ESD) robustness of multifinger MOSFET in 28-nm high-k/metal gate CMOS process was investigated in this paper. Verified in silicon, the multifinger MOSFET without the pickup structure inserted into its source region can sustain the higher ESD level and more compact layout area.
Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High-k/Metal Gate CMOS Process
(2015-04-01)
Lin, Chun-Yu
;
Chang, Pin-Hsin
;
Chang, Rong-Kun
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A pMOS device with an embedded silicon-controlled rectifier to improve its electrostatic discharge (ESD) robustness has been proposed and implemented in a 28-nm high-k/metal gate CMOS process. An additional p-type ESD implantation layer was added into the pMOS to realize the proposed device. The experimental results show that the proposed device has the advantages of high ESD robustness, low holding voltage, low parasitic capacitance, and good latchup immunity. With better performances, the proposed device was more suitable for ESD protection in a sub-50-nm CMOS process.
Study on the ESD-Induced Gate-Oxide Breakdown and the Protection Solution in 28nm High-K Metal-Gate CMOS Technology
(2015)
Lin, Chun-Yu
;
Ker, Ming-Dou
;
Chang, Pin-Hsin
;
Wang, Wen-Tai
;
電子工程學系及電子研究所
To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.
Vertical SCR Structure for On-Chip ESD Protection in Nanoscale CMOS Technology
(2015)
Lin, Chun-Yu
;
Chang, Pin-Hsin
;
Chang, Rong-Kun
;
Ker, Ming-Dou
;
Wang, Wen-Tai
A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.