Browsing by Author "Chang, Po-Hsuan"

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A 10Gb/s 44.2 dB Adaptive Equalizer with Duobinary Tracking Loop in 0.18 mu m CMOS
(2014-01-01)
Chang, Po-Hsuan
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Li, An-Siou
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Tsai, Chia-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an adaptive equalizer that converts the attenuated signal into Duobinary signaling scheme, combined with automatic Duobinary tracking technique to produce high quality Duobinary signal for simplifying the Duobinary decoding process and achieving higher data rate. The adaptive equalizer uses dual gain-mode topology that allows higher gain when the received signal is highly attenuated, and allows lower power consumption when the received signals pass through low-attenuation channel. A background offset cancellation loop circuit is added to increase the clock phase margin of the equalizer. The chip is fabricated in 0.18 mu m CMOS technology and operates at data rate of 10 Gb/s. The measurement results show that the equalizer recovers data properly for FR-4 trace with length ranging from 3 inches to 66 inches. The equalizer achieves clock phase margin of 58 % for 66-inch channel with BER less than 10(-12) and consumes power of 28.4 mW under high gain mode with 1.8V power supply.
A 6Gb/s 40dB Burst-Mode Digitally Adaptive Equalizer with Reference-Calibrated Overshoot Control
(2013-01-01)
You, Sheng-Kai
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Chang, Po-Hsuan
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Tsai, Chia-Ming
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a burst-mode equalizer for the communication incorporating electrical idle state which is usually used for power management. Fabricated in 0.18 mu m CMOS technology, the proposed equalizer can compensate over 90-inch microstrip on an FR4 PCB, which has a 40dB loss at 3GHz. The proposed overshoot control scheme with reference calibration can reduce offset-induced error on detections and is observed to achieve jitter improvement of 0.06UI. With the help of envelope detector and digital adaptation, the reaction time under burst-mode transmission is 5.5ns or 33bit-time. The equalizer consumes 26.7mW from a 1.8V supply and measured BER is less than 10(-12).
Constant Excess Bias Control for Single-Photon Avalanche Diode Using Real-Time Breakdown Monitoring
(2015-08-01)
Chang, Po-Hsuan
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Tsai, Chia-Ming
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Wu, Jau-Yang
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Lin, Sheng-Di
;
Kuo, Ming-Ching
A monolithic constant excess bias control circuit for single-photon avalanche diode (SPAD) in standard 0.18-mu m CMOS technology is reported. The proposed real-time breakdown monitoring technique is incorporated into a passive-quenching-active-reset circuit. A sample-and-hold circuit samples the breakdown level of SPAD through well-defined sampling phase. Following the sample-and-hold circuit, the level shifter with voltage shifting defined by predetermined excess bias provides the reset voltage of SPAD. The design operates the SPAD under constant excess bias and effectively mitigates the impact of the process-voltage-temperature variation by maintaining the optimal excess bias condition.