Browsing by Author "Chang, Ru-Wei"

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Characterization of the charge trapping properties in p-channel silicon-oxide-nitride-oxide-silicon memory devices including SiO2/Si3N4 interfacial transition layer
(2015-10-01)
Chiu, Yung-Yueh
;
Yang, Bo-Jun
;
Li, Fu-Hai
;
Chang, Ru-Wei
;
Sun, Wein-Town
The role of SiO2/Si3N4 interfacial transition (IFT) layer in the oxide-nitride-oxide (ONO) tri-layer is quantitatively analyzed for the first time by simulating the temperature and stress-accelerated retention characteristics of p-channel silicon-oxide-nitride-oxide-silicon (SONOS) devices. The ONO tri-layer is modeled as an alloy-dielectric by changing the atomic concentration of silicon, oxygen and nitrogen. It is revealed that simulated results including the IFT layer are more consistent with the experimental data than those neglecting the IFT layer. In addition, the results show that the trapped charge density in IFT layer is two times larger than in the bulk Si3N4 film, due to the oxygen atoms penetrated from SiO2 cause the extrinsic defects in the IFT layer. The energy levels of the trapped charge are continuously distributed, and the peak value is similar to 1.6 eV below the conduction band of the ONO tri-layer with a full width at half maximum of 0.45 eV. (c) 2015 The Japan Society of Applied Physics
Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal-Oxide-Semiconductor Field-Effect-Transistor Devices
(2011-04-01)
Li, Yiming
;
Lee, Kuo-Fu
;
Yiu, Chun-Yen
;
Chiu, Yung-Yueh
;
Chang, Ru-Wei
In this work, we explore for the first time dual-material gate (DMG) and inverse DMG devices for suppressing the random-dopant (RD)-induced characteristic fluctuation in 16 nm metal-oxide-semiconductor field-effect-transistor (MOSFET) devices. The physical mechanism of suppressing the characteristic fluctuation of DMG devices is observed and discussed. The achieved improvement in suppressing the RD-induced threshold voltage, on-state current, and off-state current fluctuations are 28, 12.3, and 59%, respectively. To further suppress the fluctuations, an approach that combines the DMG method and channel-doping-profile engineering is also advanced and explored. The results of our study show that among the suppression techniques, the use of the DMG device with an inverse lateral asymmetric channel-doping-profile has good immunity to fluctuation. (C) 2011 The Japan Society of Applied Physics
Study Trapped Charge Distribution in P-Channel Silicon-Oxide-Nitride-Oxide-Silicon Memory Device Using Dynamic Programming Scheme
(2013-04-01)
Li, Fu-Hai
;
Chiu, Yung-Yueh
;
Lee, Yen-Hui
;
Chang, Ru-Wei
;
Yang, Bo-Jun
In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking. (C) 2013 The Japan Society of Applied Physics