Browsing by Author "Chang, S. C."

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Copper voids improvement for the copper dual damascene interconnection process
(2008-02-01)
Wang, T. C.
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Wang, Y. L.
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Hsieh, T. E.
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Chang, S. C.
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Cheng, Y. L.
The mechanism of copper (Cu) voids formation from electro-chemical plating (ECP) followed by Cu chemical mechanical polishing (CMP) are studied in Cu dual-damascene interconnection. The formation of Cu voids at metal lines is the main problem that causes not only the failure of via-induced metal-island corrosion but also yield loss. The galvanic theory and Cu lifting mechanism are proposed to explain the dependence of Cu-void performance on the Cu grain size and the benzotriazole (BTA, C6H5N3) flow rates. In the integration process of Cu interconnects, it is found that the smaller Cu grain size in ECP conditions and less BTA flow rate in CMP processes cannot only reduce the number of Cu voids but also improve the water yield. (c) 2007 Elsevier Ltd. All rights reserved.
InN nanotips as excellent field emitters
(2008-03-24)
Wang, K. R.
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Lin, S. J.
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Tu, L. W.
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Chen, M.
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Chen, Q. Y.
Unidirectional single crystalline InN nanoemitters were fabricated on the silicon (111) substrate via ion etching. These InN nanoemitters showed excellent field emission properties with the threshold field as low as 0.9 V/mu m based on the criterion of 1 mu A/cm(2) field emission current density. This superior property is ascribed to the double enhancement of (1) the geometrical factor of the InN nanostructures and (2) the inherently high carrier concentration of the degenerate InN semiconductor with surface electron accumulation layer induced downward band bending effect that significantly reduced the effective electron tunneling barrier even under very low external field. (c) 2008 American Institute of Physics.
Interface morphology and electrical properties of bonded GaAs/GaAs wafers at different temperatures
(2012)
Chang, S. C.
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Wu, Y. S.
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Chang, N.
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材料科學與工程學系
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Department of Materials Science and Engineering
The microstructure and electrical properties of p-GaAs/n-GaAs bonded interface were investigated. It was observed that when bonding temperature increased from 600 to 800 degrees C, the thickness of oxide layer decreased. Current-voltage characteristic shows typical diode behaviors in these temperature ranges.
National Project on 45 to 32 nm Metal Oxide Semiconductor Field Effect Transistors for Next Century IC Fabrications
(2008)
Hwang, Huey-liang
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Wang, C. W.
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Chang, K. H.
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Tsai, C. H.
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Leou, K. C.
It is well known that the Taiwan Semiconductor industries play the very key roles for the worldwide IC foundry, and the advanced research of nanoelectronics is the lifeline for its long term developments. Professor Huey-liang Hwang effectively integrated the most outstanding research team and resource in Taiwan on the National Project on Nanometer CMOS Transistors for the 21 century, which is sponsored by the Ministry of Economic Affairs of ROC. A dozen of Professors from NTHU( National Tsing Hua University) with expertise at the novel materials and analysis and NCTU( National Chiao Tung University) with expertise at devices and reliability are devoted to the studies and are in collaboration with the world-wide-known company such as TSMC, and breakthrough of the key technologies of 45-32 nm technologies are achieved. The objective of this project is focused on the development of advanced metal gate/high-k MOSFET for 45 nm node generation and beyond, the efforts include the world first successful suppression the oxide/Si interfacial layer formation by using a bi-layer composite of HfO2 3.2 nm (ALD)/HfO2 1.5 nm (MBE), the results show a dielectric constant of 16 and an EOT of 1.15 nm, a Dit was estimated to be 4.6x10(11)cm(-2)eV(-1) with the leakage at Vfb-1V being 8.5x10(-6) A/cm(2). Also, the thermal stability of HfO2, HfAlOx alloy and Al2O3/HfO2 stack, prepared by ALD were compared, the incorporation of Al in alloy form gave superior characteristics by retaining an amorphous structure up to 1000 C, which suppress the leakage current and retards growth of the interfacial layer giving the least increment of EOT and interface traps. Besides, by incorporating Al into TiO2 gave an EOT value of the Al2O3/TiAlOx/Al2O3 film down to 0.8 nm. Furthermore, high selectivity was obtained via etching the HfAlO and silicon wafer with pattern using the ICP Plasma. In this project, YbSi metal gate for n-MOSFET and IrSi metal gate p-MOSFET were successfully fabricated for the HfAlON MESFET. The results showed the good effective workfunction of 4.15 and 4.9 eV and no degradation of gate dielectric current and mobility in the YbxSi/HfAlON and IrxSi/HfAlON FUSI-gates by reducing the metal diffusion at lower temperatures.
The joint usage of conventional medicine and alternative medicine for migraine in Taiwan: a ten-year retrospective study
(2009-10-01)
Chang, S. C.
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Hou, M. C.
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Hu, N. Z.
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Lo, L. C.
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Chen, Y. L.