Browsing by Author "Chang, TC"

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A distributed charge storage with GeO2 nanodots
(2004-04-05)
Chang, TC
;
Yan, ST
;
Hsu, CH
;
Tang, MT
;
Lee, JF
In this study, a distributed charge storage with GeO2 nanodots is demonstrated. The mean size and aerial density of the nanodots embedded in SiO2 are estimated to be about 5.5 nm and 4.3x10(11) cm(-2), respectively. The composition of the dots is also confirmed to be GeO2 by x-ray absorption near-edge structure analyses. A significant memory effect is observed through the electrical measurements. Under the low voltage operation of 5 V, the memory window is estimated to similar to0.45 V. Also, a physical model is proposed to demonstrate the charge storage effect through the interfacial traps of GeO2 nanodots. (C) 2004 American Institute of Physics.
A method for fabricating a superior oxide/nitride/oxide gate stack
(2004)
Chang, TC
;
Yan, ST
;
Liu, PT
;
Wang, MC
;
Sze, SM
A superior oxide/nitride/oxide (ONO) gate stack was demonstrated. High density plasma chemical vapor deposition was used to deposit the silicon nitride layer instead of the conventional low-pressure chemical vapor deposition for silicon/oxide/nitride/oxide/silicon technology. The densified nitride layer was performed by high-temperature dry oxidation to form a thermally grown blocking oxide layer on the silicon nitride rather than a deposited oxide layer. The ONO gate stack shows large memory window, high breakdown voltage, and reliable endurance characteristics, which is a potential candidate for future nonvolatile memory technology. (C) 2004 The Electrochemical Society.
A novel approach of fabricating germanium nanocrystals for nonvolatile memory application
(2004-01-01)
Chang, TC
;
Yan, ST
;
Liu, PT
;
Chen, CW
;
Lin, SH
A nonvolatile memory device embedded with Ge nanocrystal dots is fabricated by the thermal oxidation of Si0.8Ge0.2 combined with a rapid thermal annealing at 950degreesC in N-2 gas. The tunnel oxide in the nonvolatile memory is controlled to be 4.5 nm thick and embedded with 5.5 nm Ge nanocrystals. A low operating voltage, 5 V, is implemented and a significant threshold-voltage shift, 0.42 V, is observed. When the electrons are trapped in the Ge nanocrystals, the effect of Coulomb blockade prevents the injection and storage of more electrons and decreases the leakage current. Also, the retention characteristics are tested to be robust. (C) 2003 The Electrochemical Society.
A novel distributed charge storage element fabricated by the oxidation of amorphous silicon carbide
(2004)
Chang, TC
;
Yan, ST
;
Chen, YT
;
Liu, PT
;
Sze, SM
A novel distributed charge storage element fabricated by the oxidation of amorphous silicon carbide is proposed. For low-temperature oxidation processes, the oxidized SiCO gate stack shows a larger memory window due to the retainable dangling bonds with more Si-C bonding types and less Si-O bonds. Under 5 V write operation of the low-temperature oxidized SiCO stack, a 1.5 V threshold voltage shift is exhibited, which is sufficient for a memory device to define "0'' and "1.'' Also, the low-temperature oxidation process of the SiCO layer saves the thermal budget for the manufacturing processes of nonvolatile memory devices. (C) 2004 The Electrochemical Society.
A novel lightly doped drain polysilicon thin-film transistor with oxide sidewall spacer formed by one-step selective liquid phase deposition
(1999-08-01)
Shih, PS
;
Chang, CY
;
Chang, TC
;
Huang, TY
;
Peng, DZ
We have proposed and successfully demonstrated a novel process for fabricating lightly doped drain (LDD) polycrystalline silicon thin-film transistors (TFT's), The oxide sidewall spacer in the new process is formed by a simple one-step selective liquid phase deposition (LPD) oxide performed at 23 degrees C, Devices fabricated with the new process exhibit a lower leakage current and a better ON/OFF current ratio than non-LDD control devices. Since the apparatus used for LPD oxide deposition is simple and inexpensive, the new process appears to be quite promising for future high-performance poly-Si TFT fabrication.
A novel method for growing polycrystalline Ge layer by using UHVCVD
(2006-02-24)
Tu, CH
;
Chang, TC
;
Liu, PT
;
Yang, TH
;
Zan, HW
Poly-Ge grown on SiO2 substrates by using one-step ultra-high vacuum chemical vapor deposition (UHVCVD) process with thin Si nucleation layers at very low deposition temperature (350 degrees C) was demonstrated. The results demonstrated that the polycrystalline silicon (poly-Si) nucleation layer is needed for the growth of polycrystalline germanium (poly-Ge) on SiO2 substrates at low growth temperature. SEM image presents the films with uniform rain size and uniform thickness occurring in the samples. The grain size of poly-Ge is about 100 nm. The Raman shift spectrum and XRD spectrum also identified that films are high quality poly-Ge by using this method. (c) 2005 Elsevier B.V. All rights reserved.
A novel SiGe raised source/drain polycrystalline silicon thin-film transistor with improved on-current and larger breakdown voltage
(2003-03-01)
Peng, DZ
;
Chang, TC
;
Liu, CF
;
Yeh, PH
;
Liu, PT
A novel poly-Si thin-film transistor with a self-aligned SiGe raised source/drain (SiGe-RSD TFT) has been proposed and fabricated. The SiGe-RSD regions were grown selectively by the ultra-high vacuum chemical vapor deposition (UHVCVD) process designed by us at 550degreesC. The resultant transistor structure features an ultra-thin active channel region (20 nm) and a self-aligned thick source/drain region (120 nm), and is ideally suited for optimum performance. Significant improvements in electrical characteristics, such as higher turn-on current, lower leakage current and higher drain breakdown voltage have been observed in the SiGe RSD TFT, compared to its conventional TFT counterpart. Moreover, the process is simple and no additional masks are necessary, which is consistent with conventional fabrication processes.
A study of parasitic resistance effects in thin-channel polycrystalline silicon TFTs with tungsten-clad source/drain
(2003-08-01)
Zan, HW
;
Chang, TC
;
Shih, PS
;
Peng, DZ
;
Kuo, PY
With selectively-deposited tungsten film grown on source/drain regions, the parasitic source/drain resistance of thin-channel polycrystalline silicon (poly-Si) thin film transistors can be greatly reduced, leading to the improvement of device driving ability. After extracting the parasitic resistance from characteristics of devices with different channel length, the influences of parasitic resistance on device performances were discussed. A physically-based equation containing the parasitic resistance effects was derived to explain the behavior of linear transconductance under high gate voltage. Good agreements were found between calculated and measured data for both the thin-channel devices with or without tungsten-clad source/drain structure.
A W-spacer GOLD TFT with high performance and high reliability
(2002-09-26)
Zan, HW
;
Peng, DZ
;
Shih, PS
;
Chang, TC
;
Liu, PT
In this paper, we successfully fabricated Gate-Overlapped Lightly-doped Drain (GOLD) polycrystalline silicon thin-film transistors (poly-Si TFTs) with selectively deposited spacers. Under appropriate deposition conditions, tungsten (W) films can be selectively deposited on poly-Si gate electrodes to form spacers without any additional etching process. Compared to the conventional poly-Si TFTs without LDD structures, our devices effectively suppress the kink effect and the punch-through phenomenon in short-channel devices. The hot-carrier reliability of our devices is also improved due to the reduced electric field on the drain side. In addition, the transconductance of our devices is compatible to that of conventional devices. This is because the W-spacer acts as a part of gate electrode to induce channel when the device is operated under ON state. (C) 2002 Elsevier Science Ltd. All rights reserved.
Activation of carbon nanotube emitters by using supercritical carbon dioxide fluids with propyl alcohol
(2006)
Liu, PT
;
Tsai, CT
;
Chang, TC
;
Kin, KT
;
Chang, PL
This paper explores the application of supercritical carbon dioxide fluids on the field emission enhancement for vertically aligned carbon nanotubes. The typical heating process cannot effectively activate the deionized-water-rinsed carbon nanotube emitters, exhibiting poorer field emission performance, due to residual moisture uptake in the carbon nanotubes. In contrast, the field emission enhancement can be achieved significantly by applying the supercritical carbon dioxide fluids associated with 3 to 9 vol % propyl alcohol. It is found the cosolvent propyl alcohol plays a critical role in the activation efficiency of supercritical carbon dioxide fluids. A physical model is also deduced to clarify the observation. (c) 2006 The Electrochemical Society.
An efficient improvement for barrier effect of W-filled contact
(1996-02-01)
Yeh, WK
;
Chan, KY
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Chang, TC
;
Tsai, MH
;
Chen, SH
A post chemical vapor deposition of tungsten (CVD-W) treatment by N-2 plasma is proposed to suppress the WAl12 formation during subsequent thermal annealing, which improves the thermal stability of W-filled contact. Selective CVD-W is employed to fill the contact hole. Following W deposition, in situ N-2 plasma treatment is performed prior to Al alloy metallization. It is shown that this post CVD-W treatment efficiently suppresses the formation of WAl12, resulting in an improvement of the barrier capability of W-filled contact.
An interfacial investigation of high-dielectric constant material hafnium oxide on Si substrate
(2005-09-22)
Chen, SC
;
Lou, JC
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Chien, CH
;
Liu, PT
;
Chang, TC
In this study, the hump in the capacitance-voltage (C-V) curves, variation of leakage current, interfacial layer increase, and electron trapping in non-surface treated hafnium oxide (HfO2) samples were observed and investigated. From the results of the investigation, it was found that both rapid thermal oxidation and NH3 surface treatments improved the C-V curves. In addition, it was observed that samples treated with ammonia exhibited a lower leakage current when compared with the others. From the results of the dielectric, leakage current study, a severe electron trapping effect was exhibited under higher electric field stress. Finally, the conduction mechanism in the HfO2 thin film was dominated by Frenkel-Poole emission in a high electric field. (c) 2005 Elsevier B.V All rights reserved.
Analysis of narrow width effects in polycrystalline silicon thin film transistors
(2003-01-01)
Zan, HW
;
Chang, TC
;
Shih, PS
;
Peng, DZ
;
Huang, TY
In this study, narrow width effects of polycrystalline silicon thin film transistors (poly-Si TFTs) are investigated. With reducing channel width, TFT characteristics such as. mobility, threshold voltage, and subthreshold swing are found to improve dramatically. To gain insight on the origin of the narrow width effects, a physically-based model is proposed to simulate the output characteristics of poly-Si TFTs. Excellent fitting with the experimental data is observed over a wide range of drain bias, gate bias, and channel width. Our model shows that both the deep state density and-tail state density are reduced with reducing channel width, thus accounting for the improved TFT characteristics. In addition, subthreshold swings of poly-Si TFTs with various channel widths and lengths are compared. It is found that the subthreshold swings of poly-Si TFTs with the same channel area are identical, indicating that the grain-boundary trap density is reduced due to the reduction of channel area.
Anomalous selective tungsten growth by chemical vapor deposition
(1996)
Mei, YJ
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Chang, TC
;
Sheu, JD
;
Yeh, WK
;
Pan, FM
Selective tungsten chemical vapor deposition (W-CVD) is one of the most attractive technique for filling deep submicron contact hole and via hole for the ULSI application. In this work, we firstly find out the anomalous selective W growth for the contact hole. The tungsten only nucleates from the side ring of the contact hole bottom. Several predeposition treatments prior to W growth can improve this anomalous feature and excellently selective W growth can be achieved. Auger electron spectroscopy (AES) is utilized to investigate the interface of Si/W. A model has been proposed to explain this anomalous selective tungsten growth.
Atomic force microscopy study on the surface structure of oxidized porous silicon
(1996-08-01)
Young, TF
;
Huang, IW
;
Yang, YL
;
Kuo, WC
;
Jiang, IM
We study the surface structure of porous silicon (PS) using atomic force microscopy (AFM), before and after oxidation in a HNO3 solution. The AFM image shows the PS surface with a self-affine random fractal structure of wires, hillocks and voids in various scales. After oxidization the wires and hillocks of PS structures are glazed with oxide and the voids are filled, PS structure is altered to a simple self-affine fractal structure of hillock clusters. The fractal dimension D of PS is around 2.3, which decreases with increasing oxidization to about 2.0 of a smooth surface for the saturated oxidization. Our direct observation of the fractal structure of PS from AFM data reveals a good explanation for the recently found novel nonlinear de-response in Ag thin films deposited on PS. We find the fractal surface structure of oxidized PS responds to the stepwise avalanche electric breakdown of the resistivity of Ag thin films deposited on oxidized PS.
Characteristics and stress-induced degradation of laser-activated low temperature polycrystalline silicon thin-film transistors
(2003-02-15)
Peng, DZ
;
Chang, TC
;
Chang, CY
;
Tsai, ML
;
Tu, CH
The characteristics and reliability of laser-activated polycrystalline silicon thin-film transistors (poly-Si TFTs) under the stress condition of drain voltage (V-d)=12 V and gate voltage (V-g)=15 V have been investigated. In spite of reducing the source/drain resistivity by using laser activation method, the leakage current (V-g<0) is larger for laser-activated poly-Si TFTs in comparison with traditional furnace-activated counterparts. It is also found that the post-stress leakage and on/off current ratio degrade much faster for laser-activated poly-Si TFTs, while the degradation rates of threshold voltage and subthreshold swing are comparable to those of traditional furnace-activated TFTs. The laser activation modifies the grain structure between drain and channel region and causes grain discontinuity extending from the drain side to the channel region. The grain discontinuity near drain side in the polysilicon film has been investigated by transmission electron microscopy analysis. The effective trap state density calculated from typical I-V curve has been compared for laser-activated and furnace-activated TFTs. As a result, an inferior reliability with extra trap state density and larger leakage current was observed in the laser-activated poly-Si TFTs. (C) 2003 American Institute of Physics.
Characterization and reliability of lightly-doped-drain polysilicon thin-film transistors with oxide sidewall spacer formed by one-step selective liquid phase deposition
(2000-10-01)
Shih, PS
;
Chang, TC
;
Huang, TY
;
Yeh, CF
;
Chang, CY
We have proposed and successfully demonstrated a novel process for fabricating a lightly doped drain (LDD) polysilicon thin-film transistor (poly-Si TFT). The oxide sidewall spacer in the new process is formed by a simple one-step selective liquid phase deposition (LPD) at 23 degreesC. In contrast with conventional methods, this new process does not require an additional photolithographic step for defining the non-self-aligned offset gate, or the deposition of an oxide layer and subsequent etch-back to form the: self-aligned sidewall spacer. Devices fabricated by the new process have a lower leakage current and a better ON/OFF current ratio, compared with non-LDD control devices. The new device also shows excellent current saturation characteristics at high bias and better has hot-carrier endurance. Since the apparatus used for LPD oxide deposition is simple and inexpensive, the new process appears to be promising for future high-performance poly-Si TFT fabrication.
Characterization of multilayered Ti/TiN films grown by chemical vapor deposition
(1998-11-02)
Hu, JC
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Chang, TC
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Chen, LJ
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Yang, YL
;
Chang, CY
The resistivity of multilayered Ti/TiN films grown by chemical vapor deposition can be reduced from 240 mu Omega cm (standard sample) to 120 mu Omega cm with NH3 plasma post-treatment for 300 s. Increasing the number of multilayered Ti/TiN mu ms of reduced thickness and a plasma post-treatment technique contributed to reducing the resistivity of TiN films effectively. Smooth multilayered Ti/TiN films were observed by XTEM image. The content of chlorine in the multilayered Ti/TiN film was 1.6 at.%. Therefore, corrosion in the subsequent Al film should be minimized. SIMS depth profiles of the multilayered Ti/TiN sample showed that Ti atom distribution is fairly uniform. The result is in agreement with the observation of XTEM and the measurement of AES depth profiles. The resistivity of multlayered Ti/TiN films can be further reduced to 75 mu Omega cm with an in situ NH3 plasma post-treatment (500 W) for 300 s followed by RTA at 900 degrees C for 60 s. Therefore, low resistivity (<100 mu Omega cm) and low Cl concentration (<2 at.%) CVD TiN films can be achieved by a combination of forming a multilayered Ti/TiN structure, and using NH3 plasma post-treatment and RTA. (C) 1998 Elsevier Science S.A. All rights reserved.
Characterization of porous silicate for ultra-low k dielectric application
(2002-07-01)
Liu, PT
;
Chang, TC
;
Hsu, KC
;
Tseng, TY
;
Chen, LM
Thermal stability of a porous low-k film is a critical issue for application consideration in the back-end-of-line. In this study, thermal stability of the porous silicate has been investigated by changing the thermal processing temperatures. Experimental results have shown that the dielectric constant of the porous silicate still remains below 2.0 after thermal processing at 500 degreesC for I h. A series of material analysis techniques and electrical characteristics have been used to verify the physical and chemical characteristics of the porous silicate film. (C) 2002 Elsevier Science B.V. All rights reserved.
Characterization of Si1-x-yGexCy films grown by C+ implantation and subsequent pulsed laser annealing
(1999-07-15)
Luo, JS
;
Lin, WT
;
Chang, CY
;
Shih, PS
;
Pan, FM
Epitaxial Si1-x-yGexCy films have been grown by C+ implantation into Si0.76Ge0.24 films with a dose of 1.0 x 10(16)/cm(2) and subsequent pulsed KrF laser annealing at an energy density of 0.3-1.6 J/cm(2). Upon laser annealing Ce segregation to the film surface and diffusion to the underlying Si appeared at energy densities above 0.8 J/cm(2) and 1.4 J/cm(2), respectively while the depth profiles of C remained nearly unchanged as in the as-implanted Si1-x-yGeyCy film. Concurrently, no SiC and twin were observed. The amount of C incorporated into substitutional sites initially increased with the energy density in the range of 0.3-1.0 J/cm(2), and then saturated at an energy density of 1.0-1.6 J/cm(2). For the Si1-x-yGexCy films grown at 1.0 J/cm(2) for 5 and 20 pulses SiC was formed with its amount increasing with the pulse number because of C segregation to the film surface and the original amorphous/crystal interface where the EOR defects were present. For the Si1-x-yGexCy films grown at energy densities below 1.0 J/cm(2) the reduction of tensile stress mainly resulted from the effect of substitutional carbon incorporation. (C) 1999 Elsevier Science S.A. All rights reserved.