Browsing by Author "Chang, TS"

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A memory-efficient realization of cyclic convolution and its application to discrete cosine transform
(2005-03-01)
Chen, HC
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Guo, JI
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Chang, TS
;
Jen, CW
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電子工程學系及電子研究所
This paper presents a memory-efficient approach to realize the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic (DA) computation, exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel, separate the kernel to be two perfect cyclic forms, and partition he content of ROM into groups to facilitate an efficient realization of a one-dimensional (1-D) N-point DCT kernel using (N-1)/2 adders or substractors, one small ROM module, a barrel shifter, and ((N - 1)/2) + 1 accumulators. The proposed memory-efficient design technique is characterized by rearranging the content of the ROM using the conventional DA approach into several groups such that all the elements in a group can be accessed simultaneously in accumulating all the DCT outputs for increasing the ROM utilization. Considering an example using 16-bit coefficients, the proposed design can save more than 57% of the delay-area product, as compare with the existing DA-based designs in the case of the 1-D seven-point DCT. Finally, a 1-D DCT chip was implemented to illustrate the efficiency associated with the proposed approach.
A multiplierless reconfigurable resizer for multi-window image display
(1997-01-01)
Huang, CM
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Chang, TS
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Jen, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a real-time resizing IC that can dynamically reconfigure the multiplierless polyphase CIC (cascaded-integer-comb) filter modules to meet even non-integer resizing ratio. The IC can process four 320x200 30 frames/sec at 55 Mhz clock.
A multiplierless reconfigurable resizer for multi-window image display
(1997-08-01)
Huang, CM
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Chang, TS
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a real-time resizing IC that can dynamically reconfigure the multiplierless polyphase CIC (cascaded-integer-comb) filter modules to meet even noninteger resizing ratio. The hardware cost is greatly reduced by using overlap-save based block input and concurrent register reset scheme. The simulated results show that this chip can process four 320x200 30 frames/sec at 55 MHz clock.
A simple processor core design for DCT/IDCT
(2000-04-01)
Chang, TS
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Kung, CS
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Jen, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a cost effective processor core design that features the simplest hardware and is suitable for discrete cosine transform/indiscrete cosine transform (DCT/IDCT) operations in H.263 and digital camera. This design combines the techniques of fast direct two dimensional DCT algorithm, the bit-level adder-based distributed arithmetic, and common subexpression sharing;to reduce the hardware cost and enhance the computing speed. The resulting architecture is very simple and regular such that it can be easily scaled for higher throughput rate requirements. The DCT design has been implemented by 0.6 mu m SPDM CMOS technology and only costs 1493 gate count, or 0.78 mm(2), The proposed design can meet real-time DCT/IDCT requirements of H.263 codec system for QCIF image frame size at 10 frames/s with 4:2:0 color format. Moreover, the proposed design still possesses additional computing power for other operations when operating at 33 Mhz.
An hardware efficient deblocking filter for H.264/AVC
(2005)
Cheng, CC
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Chang, TS
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an efficient VLSI architecture for the deblocking filter in H.264/AVC standard. The computing flow is reordered for easy hardware implementation. The resulting design can achieve 100 MHz with only gate count of 9.16K when synthesized from verilog RTL design by using UMC 0.18 mu m CMOS technology. When clocked at 82.58MHz, our design can easily support real-time deblocking of 2Kx1K@30Hz video application, this high performance can meet high resolution real-time application requirement.
Architecture design of MPEG-4 texture decoder - Supporting object-based video coding
(2005)
Hsu, HC
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Chang, NYC
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Chang, TS
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Handling of the complexity which arises due the irregularity data nature for MPEG-4 object based video coding is an important issue in MPEG-4 texture decoder design. Another crucial issue is designing an efficient architecture to satisfy the resource sensitive nature of portable embedded video codec systems. This paper presents an architecture for texture decoding to address these two major issues. By adopting zero-skipping and zero index tables together, the throughput and power consumption are improved significantly. To avoid incurring extra hardware overhead, multiplication sharing and buffer sharing are also incorporated. ne synthesized design can perform texture decoding of CIF@30FPS under 2.18 MHz. using UMC 0.181 mu m 1P6M technology, the reported power consumption is 0.92 mW.
Combined frame memory architecture for motion compensation in video decoding
(2005)
Chang, TS
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Chang, TS
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a combined frame memory architecture which is smaller in size and is potential in reducing power consumption compared to the most commonly used ping-pong frame memory. The combined frame memory maps both reference frame data and current frame data onto one single frame memory instead of two in ping-pong architecture. Together with the characteristic of high percentage of MBs with zero-valued MVs and no residual, the combined frame memory architectures is evaluated to be able to reduce not only the memory size, but also the average energy consumption and memory access latency for applications like surveillance, video phone, and video conference. According to the statistics and analysis result, the proposed combined frame memory architecture memory size is only 57% compared to ping-pong architecture. The proposed combined frame memory architecture can reduce up to 83% of average latency and 39% of average power consumption compared to pin-pong frame memory architecture.
Distributed arithmetic realisation of cyclic convolution and its DFT application
(2005-12-01)
Chen, HC
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Guo, JI
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Jen, CW
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Chang, TS
;
電子工程學系及電子研究所
The authors present a new hardware-efficient group distributed arithmetic (GDA) design approach for the one-dimensional (1-D) discrete Fourier transform (DFT). The approach adopts distributed arithmetic (DA) computation and exploits the good features of cyclic convolution to facilitate an efficient realisation of the 1-D N-point DFT using small ROM modules. a barrel shifter, and N accumulators. The proposed GDA design is achieved by rearranging the contents of the ROM into several groups such that all the elements in a group can be accessed simultaneously in accumulating all the DFT outputs to increase ROM utilisation. Moreover, combining the symmetrical property of the DFT coefficients with the proposed GDA design requires only half the ROM contents to be stored, which further reduces ROM size by a factor of two. Realisation of a long-length DFT formulated in cyclic convolution is based on data permutation of the rows and columns in the matrix to directly partition the long-length cyclic convolution into short ones, so that short length DFTs may be realised efficiently by the proposed GDA design to achieve low hardware cost. This design approach is termed the 'block-based group distributed arithmetic approach. Compared with existing systolic array designs and DA-based designs. the proposed GDA design can reduce the delay-area product by 29%-68% based on a 0.35 mu m CMOS cell library.
Fast block type decision algorithm for intra prediction in H.264 FRext
(2005)
Lin, YK
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Chang, TS
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a fast block type decision algorithm for 4x4, M and 16x16 intra prediction in H.264/AVC FRExt (Fidelity Range Extension). With additional M intra prediction size, the complexity of intra prediction is increased by almost 50%. Thus, the proposed algorithm uses the smoothness of the macroblock to select the intra prediction block size and save computational cost. When further combining with our previously proposed three-step fast intra prediction algorithm, the proposed algorithm can save up to 32.1% and 63.4% of computation time of all I frames and intra prediction coding respectively, and achieves average 1.05% bit rate decrease and 0.046 dB quality degradation when comparing with the reference software.
Fast motion estimation by adaptive early termination
(2005)
Al-Qaralleh, EA
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Chang, TS
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電機學院
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College of Electrical and Computer Engineering
This paper presents a fast motion estimation (ME) algorithm by adaptively changing the early termination threshold for the current accumulated partial SAD value. The simulation results show that the proposed algorithm can provide the similar quality while save 77.9% and 50.6% of SAD computation when comparing with that in MTEG-4 VM18.0 and H.264 JM9.0, respectively.
Fast three step intra prediction algorithm for 4x4 blocks in H.264
(2005)
Cheng, CC
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Chang, TS
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a fast three step algorithm for H.264 4x4 intra prediction. Motivated by the highly correlation of RD cost between different prediction direction, in each step of the algorithm, the proposed algorithm efficiently explores the neighborhood direction around the minimum one and thus skips other unlikely ones. Thus, the proposed algorithm can complete 4x4 intra prediction by only examining 6 modes instead of 9 modes in the full search algorithm. The simulation result shows that the proposed algorithm can maintain the similar PSNR quality to the full search algorithm with only about 1% bit-rate increase.
Hardware efficient transform designs with cyclic formulation and subexpression sharing
(1998)
Chang, TS
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Jen, CW
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電機學院
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電子工程學系及電子研究所
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College of Electrical and Computer Engineering
This paper presents a hardware efficient architecture for transform designs. Unlike other designs that use systolic array and memory-based design, the proposed architecture exploited the constant property of the transform coefficients as well as their numerical property. The proposed design reformulates the transform with cyclic convolution such that filter type subexpression sharing can be applied to reduce the area cost. The results show that the new designs can save up to 81% gate area cost compared with previous designs for 5-point DFT designs.
Hardware-efficient DFT designs with cyclic convolution and subexpression sharing
(2000-09-01)
Chang, TS
;
Guo, JI
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a hardware efficient design for the discrete Fourier transform (DFT), The proposed design not only applies the constant property, but also exploits the numerical property of the transform coefficients. DFT is first formulated as cyclic convolution form to make each DFT output sample computations have the same computation kernels. Then, by exploring the symmetries of DFT coefficients, the word-level hardware sharing can be applied, in which two times the throughput is obtained. Finally, bit-level common subexpression sharing can be efficiently applied to implement the complex constant multiplications by using only shift operations and additions. Though the three techniques have been proposed separately for transform, this paper integrates the above techniques and obtains additive improvements. The I/O channels in our design are limited to the two extreme ends of the architecture that results in low I/O bandwidth. Compared with the previous memory-based design, the presented approach can save 80% of gate area with two-times faster throughput for length N = 61. The presented approach can also be applied to power-of-two length DFT Similar efficient designs can be obtained for other transforms like DCT by applying the proposed approach.
Hardware-efficient implementations for discrete function transforms using LUT-based FPGAs
(1999-11-01)
Chang, TS
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Jen, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The multiplier-free design of transforms implemented in LUT-based FPGAs is presented. To fit bit-level grain size in the FPGA device at algorithm level the authors use modified distributed arithmetic (DA) and a named adder-based DA to formulate bit-level transform expressions, then they further minimise hardware cost by the proposed vertical subexpression sharing. For implementation, the required input buffer design is also considered by employing FPGA device characteristics and cyclic formulation. The proposed design can offer savings in excess of two-thirds of hardware cost compared with ROM-based DA.
Hardware-efficient pipelined programmable FIR filter design
(2001-11-01)
Chang, TS
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Jen, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
With the increasing demand for video-signal processing and transmission. high-speed programmable FIR filters are required for real-time processing. This paper presents a hardware-efficient pipelined FIR architecture with programmable coefficients. FIR operations are first reformulated into multi-bit DA form at an algorithm level. Then, at the architecture level, the (p, q) compressor, instead of Booth encoding or RAM implementation, is used for high-speed operation. Due to the simple architecture, we can easily pipeline the proposed FIR filter to the adder level and save up to half of the cost of previous designs without sacrificing performance. The presented design is useful for bit-parallel input design, which can save 36.7% of the area cost compared with previous approaches.
Integration issues for siloxane-based hydrogen silsesquioxane (HSQ) applied on TFT-LCDs
(2006-03-01)
Chang, TS
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Chang, TC
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Liu, PT
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Chang, TS
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Yeh, FS
In this study, a low-k material, siloxane-based hydrogen silsesquioxane (HSQ) has been investigated for a passivation dielectric between the transistor and pixel levels in thin-film transistor (TFT) arrays. The characteristics of low-k dielectric film have been studied, especially under visible light illumination and electric operation. Compared with the conventional nitride film (k similar to 7), the HSQ passivation layer (k similar to 2.8) not only lowers the RC time delay in device, but also enhances the brightness of thin-film transistors liquid crystal displays (TFT-LCDs). (c) 2005 Published by Elsevier B.V.
Low power FIR filter realization with differential coefficients and input
(1998)
Chang, TS
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Jen, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Most FIR filter realizations use the inputs and coefficients directly to compute the convolution. In this paper, we present a low power and high speed FIR filter designs by using first order difference between inputs and various orders of differences between coefficients. This design first reformulates the FIR operations with the differences in algorithm level. Then, ill architecture level, we adopt the DA architecture to exploit the probability distribution such that power consumption can be reduced further. The design is applied to an example FIR filter to quantify the energy savings and speedup. It shows lower power consumption than the previous design with the comparable performance.
Low-power FIR filter realization with differential coefficients and inputs
(2000-02-01)
Chang, TS
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Chu, YH
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Jen, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This brief presents a low-power finite-impulse response filter design by using differential coefficients and inputs instead of using them directly such that fewer bits are required, thereby reducing the size of arithmetic units and power dissipation. Ne present an improved algorithm to effectively generate differential coefficients so that the differential coefficients methods can be applied to full bandwidth (BW) of filters instead of only narrow-band filters in previous approaches. Simulations with fixed coefficient filters indicate reduction in transition activity ranging from 1-53% over the full range of filter BW's, The presented results can be applied to adaptive filters to generate suitable differential coefficients.
Multi-station analysis of surface wave dispersion
(2004-12-01)
Lin, CP
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Chang, TS
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土木工程學系
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Department of Civil Engineering
Methods based on multi-station recordings are presented for constructing the experimental dispersion curve of Rayleigh waves. Multi-station recording permits a single survey of a broad depth range, high levels of redundancy with a single field configuration, and the ability to adjust the offset, effectively reducing near field and far field effects. A method based on the linear regression of phase angles measured at multiple stations is introduced for determining data quality and filtering criteria. This method becomes a powerful tool for on site quality control in, real time. The effects of multiple modes and survey line parameters, such as near offset, receiver spacing, and offset range, are investigated. Parametric studies result in,general guidelines for the field data acquisition. A case study demonstrates how to easily deploy commonplace seismic refraction equipment to simultaneously record data for P-wave tomographic interpretation and multi-station analysis of surface wave. (C) 2004 Elsevier Ltd. All rights reserved.
New distributed arithmetic algorithm and its application to IDCT
(1999-08-01)
Chang, TS
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Chen, C
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Jen, CW
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Distributed arithmetic (DA) has been widely used to implement inner product computations with a fixed input. Conventional ROM-based DA suffers from large ROM requirements. A new DA algorithm is proposed that expands the fixed input instead of the variable input into bit level as in ROM-based DA. Thus the new DA algorithm can take advantage of shared partial sum-of-products and sparse nonzero bits in the fixed input to reduce the number of computations. Unlike ROM-based DA that stores the precomputed results the new DA algorithm uses a predefined structure to compute results. When applied to a 1-D eight-point DCT system the new DA algorithm only needs 30% of hardware area and has faster speed as compared with ROM-based DA. To illustrate the efficiency of the proposed algorithm a 2-D IDCT chip was implemented using 0.8 mu m SPDM CMOS technology. The chip with size 4575 x 5525 mu m can deliver a processing rate of 50 Mpixels per second.