Browsing by Author "Chang, TY"

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A new observation of the germanium outdiffusion effect on the hot carrier and NBTI reliabilities in sub-100nm technology strained-Si/SiGe CMOS devices
(2005)
Chung, SS
;
Liu, YR
;
Yeh, CF
;
Wu, SR
;
Lai, CS
In this paper, the evidence of SiGe layer induced trap generation and its correlation with enhanced degradation in strained-Si/SiGe CMOS devices have been reported for the first time. First, a new two-level charge pumping(CP) curve has been demonstrated to identify the Ge out-diffusion effect. Secondly, enhanced degradation in strained-Si devices has been clarified based on experimental results. Both n- and p-MOSFE's exhibit different extent of HC degradation effect. This is attributed to the difference in their mobility enhancement as well as additional traps coming from the Si/SiGe interface. Finally, temperature dependence of HC and NBTI has been examined for both strained-Si and bulk devices. Sophisticated measurement techniques, charge pumping and gated-diode (GD) measurements, have been employed to understand the generated interface traps. Results show that strained-Si device is less sensitive to the temperature and has a chance for better NBTI reliability if we have a good control of the strained-Si/SiGe interface, such as through low temperature gate oxide process or better S/D junction formation.
A novel process-compatible fluorination technique with electrical characteristic improvements of poly-Si TFTs
(2005-06-01)
Wang, SD
;
Lo, WH
;
Chang, TY
;
Lei, TF
;
電子工程學系及電子研究所
A process-compatible fluorine passivation technique of poly-Si thin-film transistors (TFTs) was demonstrated by employing a novel CF4 plasma treatment. Introducing fluorine atoms into poly-Si films can effectively passivate the trap states near the SiO2/poly-Si interface. With fluorine incorporation, the electrical characteristics of poly-Si TFTs can be significantly improved including a steeper subthreshold slope, smaller threshold voltage, lower leakage current, higher field-effect mobility, and better On/Off current ratio. Furthermore, the CF4 plasma treatment also improves the reliability of poly-Si TFTs with respect to hot-carrier stress, which is due to the formation of strong Si-F bonds.
A threshold signature scheme for group communications without a shared distribution center
(2004-08-01)
Chang, TY
;
Yang, CC
;
Hwang, MS
;
資訊工程學系
;
Department of Computer Science
In this paper, we shall propose a (t, n) threshold signature with (k, l) threshold-shared verification to be used in a group-oriented cryptosystem without a shared distribution center (SDC). In this scheme, any t participants can represent a group (signing group) to sign a message, and any k participants can represent another group (verifying group) to verify the signature. We need no SDC to distribute the public and private keys to all the participants in the two groups. Hence, our scheme is more practical in real-world applications and more efficient than its predecessors in terms of communication and computational complexity as well as storage. (C) 2003 Elsevier B.V. All rights reserved.
An improvement of the Yang-Shieh password authentication schemes
(2005-03-25)
Yang, CC
;
Wang, RC
;
Chang, TY
;
資訊工程學系
;
Department of Computer Science
Recently, Yang and Shieh proposed two password authentication schemes by employing smart cards. One is a timestamp-based password authentication scheme and the other is a nonce-based password authentication scheme. In 2002, Chan and Cheng pointed Out that Yang and Shieh's timestamp-based password authentication scheme was vulnerable to the forgery attack. However, in 2003, Sun and Yell pointed Out that Chan and Cheng's attack was unreasonable. At the same time, Sun and Yell pointed out that Yang and Shieh's password authentication schemes were still Vulnerable to the forgery attack. In this paper, we shall improve Yang and Shieh's schemes to resist Sun and Yell's attack. (C) 2004 Elsevier Inc. All rights reserved.
An improvement on the Lin-Wu (t, n) threshold verifiable multi-secret sharing scheme
(2005-04-05)
Chang, TY
;
Hwang, MS
;
Yang, WP
;
資訊工程學系
;
Department of Computer Science
Lin and Wu [IEE Proc. Comput. Digit. Tech. 146 (1999) 264] have proposed an efficient (t, n) threshold verifiable multi-secret sharing (VMSS) scheme based on the factorization problem and the discrete logarithm modulo a large composite problem. In their scheme, the dealer can arbitrarily give any set Of multiple secrets to be shared, and only one reusable secret shadow is to be kept by every participant. On the other hand, they have claimed that their scheme can provide an efficient solution to the cheating problems between the dealer and any participant. However, He and Wu [IEE Proc. Comput. Digit. Tech. 148 (2001) 139] have shown that Lin and Wu's scheme is in fact insecure against a cheating participant. In this paper, we shall try to improve the security of Lin and Wu's scheme while providing more efficient performance than other VMSS schemes in terms Of computational complexity. (C) 2004 Elsevier Inc. All rights reserved.
An investigation of scanning capacitance microscopy on iron-contaminated p-type silicon
(2001-09-01)
Chang, MN
;
Chang, TY
;
Pan, FM
;
Wu, BW
;
Lei, TF
Scanning capacitance microscopy (SCM) is employed to examine iron-contaminated p-type Si samples. For slightly contaminated samples, a dc voltage of -0.8 V, applied between the sample and the conductive tip, induces positive trapped charges. Owing to the existence of these charges, the region containing trapped charges exhibits an obviously low dC/dV signal. According to contact-mode atomic force microscopy results, the surface, morphology has little effect on the SCM signal. The experimental results indicate that SCM is capable of detecting the distribution of oxidation-related. defects which cannot otherwise be easily observed by atomic force microscopy and transmission electron microscopy. (C) 2001 The Electrochemical Society.
Broadcasting cryptosystem in computer networks using geometric properties of lines
(2002-05-01)
Hwang, MS
;
Lee, CC
;
Chang, TY
;
資訊工程學系
;
Department of Computer Science
In 1997, Wu and Wu proposed an improvement of the Chang-Wu broadcasting cryptosystem using geometric properties of lines. The Wu-Wu scheme gave a better performance and required fewer public parameters than the Chang-Wu scheme. In this paper the authors propose an improvement to the Wu-Wu scheme using geometric properties of line. This improvement reduces the computation and significantly decreases the parameters required as compared to the Wu-Wu scheme.
Cryptanalysis of publicly verifiable authenticated encryption
(2004-06-01)
Chang, TY
;
Yang, CC
;
Hwang, MS
;
資訊工程學系
;
Department of Computer Science
Recently, Ma and Chen proposed a new authenticated encryption scheme with public verifiability. The signer can generate a signature with message recovery for a specified recipient. With a dispute, the recipient has ability to convert the signature into an ordinary one that can be verified by anyone without divulging her/his private key and the message. However, we point out that any adversary can forge a converted signature in this article.
Cryptanalysis of simple authenticated key agreement protocols
(2004-08-01)
Yang, CC
;
Chang, TY
;
Hwang, MS
;
資訊工程學系
;
Department of Computer Science
In this article, we will present a modification attack and a dictionary attack to subvert the security of the Tseng scheme and the Ku-Wang scheme. As we know, no existing schemes of simple authenticated key agreement protocols can successfully withstand our modification attack.
Cryptanalysis of the improved authenticated key agreement protocol
(2005-12-15)
Chang, TY
;
Yang, CC
;
Yang, YW
;
資訊工程學系
;
Department of Computer Science
Hsu et al. recently pointed out that the Ku-Wang scheme is vulnerable to modification attack and further proposed an improvement on their scheme. However, this article will show the improvement which they claim is still vulnerable by off-line password guessing attack. (c) 2005 Published by Elsevier Inc.
Drain/gate-voltage-dependent on-current and off-current instabilities in polycrystalline silicon thin-film transistors under electrical stress
(2005-09-01)
Wang, SD
;
Chang, TY
;
Lo, WH
;
Sang, JY
;
Lei, TF
The On-current (I(on)) and Off-current (I(off)) instabilities of polycrystalline silicon thin-film transistors (poly-Si TFTs) were investigated under various stress conditions. The stress-induced device degradation was studied by measuring the dependences Of I(on) and I(off) on the drain/gate voltages. From the results, dissimilar variations in I(on) and I(off) were observed. The differences can be attributed to the variances in the amount of trap charges in the gate oxide and the spatial distributions of the trap states generated in the poly-Si channel. A comprehensive model for the degradation Of I(on) and I(off) in poly-Si TFTs under various electrical stress conditions was suggested.
Effect of CF4 plasma pretreatment on low temperature oxides
(2002-12-01)
Chang, TY
;
Chen, HW
;
Lei, TF
;
Chao, TS
;
電子工程學系及電子研究所
This study describes a novel technique for forming low temperature oxides (<350 degreesC) using a replacement metal gate process. Low temperature oxides were generated by N2O plasma in a PECVD system with pretreatment in CF4. Fabricated oxides demonstrate excellent current-voltage (I-V) characteristics, such as low leakage current, high breakdown charge and good reliability. Experimental results indicate that CF4 plasma treatment can significantly improve the mobility and resistance against hot carrier stress of MOSFETs. With excellent electrical properties, this technique is suitable for fabrication low temperature devices.
Growing high-performance tunneling oxide by CF4 plasma pretreatment
(2003-01-01)
Chang, TY
;
Lee, JW
;
Lei, TF
;
Lee, CL
;
Wen, HC
Thin tunneling oxides grown on a CF4 pretreated silicon substrate were prepared and investigated for the first time. The tunneling current of the CF4-treated oxide is about three orders of magnitude higher than that of thermal oxide; furthermore, the stress-induced anomalous current and low electric field leakage current were greatly suppressed. The improvement was attributed to the incorporation of fluorine in the oxide region. Both control and CF4-treated devices exhibited comparable channel mobility. However, pretreatment with CF4 markedly improved the reliability of the insulator. This oxide is highly promising for fabricating low-voltage electrically erasable and programmable read-only memories (EEPROMs) without increasing the complexity of the process. (C) 2002 The Electrochemical Society.
Impact of nitrogen and/or fluorine implantation on deep-submicron Co-salicide process
(2002-08-01)
Chang, TY
;
Lei, TF
;
Chao, TS
;
Chen, SW
;
Kao, LM
In our previous study, using NF3 annealed poly-Si to improve gate oxide integrity for Co-silicide process has been proposed [SSDM, 1998, p. 164]. It is very interesting and important to know the mechanism of both F and N incorporation in the SiO2 and Co-salicide. In this study, F and/or N will be implanted into poly-Si with/without Co-salicide process, to identify the interaction of N and F in the SiO2 and Co-salicide process. In our work, we will describe the optimized structure and F/N incorporation for Co-silicide process. (C) 2002 Elsevier Science Ltd. All rights reserved.
Improvement of low-temperature gate dielectric formed in N2O plasma by an additional CF4 pretreatment process
(2002-07-01)
Chang, TY
;
Lei, TF
;
Chao, TS
;
Wen, HC
;
Chen, HW
This study describes a novel technique to form low temperature oxide (<350 &DEG;C). Low-temperature oxides were formed by N2O plasma in the plasma-enhanced chemical vapor deposition (PECVD) system with a CF4 pretreatment. These oxides demonstrate excellent current-voltage (I-V) characteristics comparable to thermally grown oxides. Experimental results indicate that CF4 plasma treatment can significantly improve the reliability of low-temperature oxides. With excellent electrical properties, the technique is highly promising for low-temperature processes.
Improvement of ultra-thin 3.3 nm thick oxide for co-salicide process using NF3 annealed poly-gate
(1999-04-01)
Chang, TY
;
Lei, TF
;
Chao, TS
;
Huang, CT
;
Chen, SK
To get high quality ultra-thin oxide is very important and difficult for IC industry now. Using NF3 annealed poly-Si gate to improve gate oxide integrity is described. However, reducing fate, source and drain parasitic resistance with gate lengths down to 0.2 mu m is another key point. Co-salicide process can successfully reduce the gate resistance even for a gate length of 0.075 mu m. Although, Co-salicide process has a leakage problem. Using NF3 annealing to prevent Co diffusing into gate oxide is described too. Results show that the optimal NF3 annealing significantly improves electrical characteristics of ultra-thin oxide and Co-salicide process in terms of leakage current and breakdown field, as compared to the samples without NF3 annealing.
Improvement on pretty-simple password authenticated key-exchange protocol for wireless networks
(2004)
Chang, TY
;
Yang, CC
;
Chen, CM
;
資訊工程學系
;
Department of Computer Science
This paper presents an improved method inspired by the recently proposed Pretty-Simple PAKE (Password Authenticated Key-Exchange) protocol, which is already a well-known, robust and simple password authenticated key exchange scheme. In our even more efficient scheme, only the password needs to be negotiated in advance, and the computations have also been simplified. Our scheme is based on the elliptic curve discrete logarithm problem and can gain the benefit from the key block size, speed and security. Since our new scheme is both efficient and fast with a low cost for device storage, it is especially suitable for the wireless network environment.
Mechanism of on-current and off-current instabilities under electrical stress in polycrystalline silicon thin-film transistors
(2005)
De Wang, S
;
Chang, TY
;
Lo, WH
;
Lei, TF
;
電子工程學系及電子研究所
The On-current (I(on)) and Off-current (I(off)) instabilities of polycrystalline silicon thin-film transistors (poly-Si TFTs) were investigated under various electrical stress conditions. The stress-induced device degradation was studied by measuring the dependences of I(on) and I(off) on the drain/gate voltages. Using this technique, dissimilar variations of I(on) and I(off) after stress were observed. The differences can be attributed to the variances in the amount of charges trapped in the gate oxide and the spatial distributions of the trap states generated in the poly-Si channel. These results suggested a comprehensive model for the I(on) and I(off) instabilities of poly-Si TFTs.
Mobile IP assistance in ad hoc routing security using geometric properties of lines
(2005-06-01)
Chang, TY
;
Yang, CC
;
Chen, CM
;
資訊工程學系
;
Department of Computer Science
Recently, the integration of wired and wireless networks has become an interesting issue. The introduction of extending Mobile IP to mobile ad hoc networks not only helps the mobile nodes connect to the Internet but also broadens the scope of the ad hoc networks and increases their application. However, these hybrid schemes faces several security problems from the inherent weakness of ad hoc routing. In this paper, we propose a hybrid authentication scheme of Mobile IP assistance for ad hoc routing security. The regular Mobile IP registration scheme has been refined to an ad hoc key-aided version and now incorporates a novel routing packet authentication mechanism in the ad hoc routing operation. A distinct character of this hybrid scheme is that a Mobile Agent can form a secure ad hoc network where the mobile hosts can be authorized and authenticated by the refined Mobile IP registration scheme. In these findings, we shall propose that the mobile hosts can follow a novel routing packet authentication mechanism to secure the routing packets by using the cryptography of the simple geometric properties of lines. Since the novel routing authentication mechanism does not need digital signatures for completing the routing packet integrity, in this hybrid authentication scheme, the cryptographic computation cost on the mobile hosts' side is relatively minimized.
Observation of differential capacitance images on slightly iron-contaminated p-type silicon
(2002-08-01)
Chang, MN
;
Chen, CY
;
Pan, FM
;
Chang, TY
;
Lei, TF
Scanning capacitance microscopy (SCM) is employed to study defect distribution induced by iron contamination on p-type silicon wafers. For slightly contaminated samples, SCM reveals that iron contamination induces interface traps in the defect region. Interface traps perturb significantly the depletion behavior of the silicon surface. Iron contamination also decreases the lifetime and increases the density of minority carriers in the defect region. The defects induced by iron contamination exhibit an obvious bias-dependent SCM contrast. By differential capacitance images, one can examine the defect density distribution. The influence of these microscale defects on the electrical characteristics of the metal oxide semiconductor (MOS) capacitor cannot be observed by conventional capacitance-voltage measurement. (C) 2002 The Electrochemical Society.