Browsing by Author "Chang, Tang-Long"

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Impact of Shielding Line on CDM ESD Robustness of Core Circuits in a 65-nm CMOS Process
(2011)
Ker, Ming-Dou
;
Lin, Chun-Yu
;
Chang, Tang-Long
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.
Investigation on CDM ESD events at core circuits in a 65-nm CMOS process
(2012-11-01)
Lin, Chun-Yu
;
Chang, Tang-Long
;
Ker, Ming-Dou
;
交大名義發表
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National Chiao Tung University
Among three chip-level electrostatic discharge (ESD) test standards, which were human-body model (HBM), machine model (MM), and charged-device model (CDM), the CDM ESD events became critical due to the larger and faster discharging currents. Besides input/output (I/O) circuits which were connected to I/O pads, core circuits also suffered from CDM ESD events caused by coupled currents between I/O lines and core lines. In this work, the CDM ESD robustness of the core circuits with and without inserting shielding lines were investigated in a 65-nm CMOS process. Verified in a silicon chip, the CDM ESD robustness of the core circuits with shielding lines were degraded. The failure mechanism of the test circuits was also investigated in this work. (C) 2012 Elsevier Ltd. All rights reserved.
Layout Styles to Improve CDM ESD Robustness of Integrated Circuits in 65-nm CMOS Process
(2011)
Ker, Ming-Dou
;
Lin, Chun-Yu
;
Chang, Tang-Long
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Due to the thinner gate oxide in the nanoscale CMOS technology and the larger chip size in the system-on-chip (SoC) IC products, the charged-device-model (CDM) electrostatic discharge (ESD) has become the major ESD events to cause failures during IC manufacturing procedures. The effective ESD protection design against CDM ESD stresses should be implemented into the chip with layout optimization to improve its ESD robustness. In this work, the impacts of different layout styles of MOS devices on CDM ESD robustness were investigated in a 65-nm CMOS process. The experimental results can provide useful information to optimize the layout of integrated circuits against CDM ESD events.