Browsing by Author "Chang, Tao-Chih"

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3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)
(2018-01-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Chen, Shang-Chun
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Chang, Hsiang-Hung
;
Chang, Tao-Chih
This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-mu m-diameter/ 50-mu m-length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12-mu m diameter are bonded using three step temperature bonding profile. Further stacked DRAM/ Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.
An RDL-First Fan-Out Panel-Level Package for Heterogeneous Integration Applications
(2019-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
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Wang, Chun-Min
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Lee, Chia-Hsin
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Huang, Shin-Yi
Technologies of Fan-outpanel-level packaging (FOPLP) are studies in this paper. First, the warpage control of a molded panel is a crucial problem for FOWLP technology development. In this paper, finite element analysis (FEA) is applied to study the influence of back end of the line (BEOL) process-induced warpage, as well as characterization for simulation, and investigation of each single process. In our process, a liquid release material is coated onto a 370 mm x 470 mm glass carrier. After baking, three layers of redistribution layer (RDL), passivation, and Cu leads are fabricated on the panel with coating, exposing, developing, lithography, and electroplating processes. Silicon test chips with a size of 16 mm x 10 mm and micro solder bumps with a pitch of 90 mu m are thinned down to 150 mu m. Test chips are then flip-chip bonded onto glass carrier with pre-bond and reflow proces. After panel molding, a laser debonding method, another key technology advancement, is utilized for panel debond. Debond performance, which is directly related to laser parameter and panel-level package (PLP) structure, is critical. After debonding, the molded panel is cleaned, followed by dicing and OSP coating processes, and then the electrical performance of the interconnection is evaluated. Reliability tests at the component level, such as pre-condition, thermal cycling test (TCT), and unbiased HAST (uHAST), are performed. The demonstration of RDL-first PLP technology without interposers proves its great potential in heterogeneous integration applications.
An RDL-First Fan-out Wafer-level Package for Heterogeneous Integration Applications
(2018-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
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Shen, Wen-Wei
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Huang, Shin-Yi
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Kuo, Tzu-Ying
Fan-out wafer-level packaging (FOWLP), a new heterogeneous integration technology, is gradually becoming an attractive solution. Compared with conventional 2.5D/3D IC structures, fan-out WLP does not use a costly interposer element and can have a thin, high-density, and low-cost IC packaging. In this study, a novel fan-out WLP with RDL-first method is demonstrated. Finite element method was used to optimize the warpage control of a reconstituted wafer and to identify the material properties and fabrication for the FOWLP. Calculation results were applied in the design of the test vehicle. Reliability testing of each component level was performed with different techniques such as temperature cycling test (TCT), high temperature storage (HTS) and thermal humidity storage test (THST). The demonstration of RDL-first WLP technology without interposer proves that it has excellent potential for heterogeneous integration applications.
Copper-to-Copper direct bonding on highly (111) oriented nano-twinned copper in no-vacuum ambient
(2017-01-01)
Juang, Jing-Ye
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Lu, Chia-Ling
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Chen, Kuan-Ju
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Chang, Tao-Chih
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Chen, Chih
In this study, we achieve the Cu-to-Cu direct bonding by using the (111) oriented nano-twined-Cu in N-2 ambient, without vacuum condition and no additional thermal annealing treatment is needed. A well bonded interface under a temperature gradient between 400 degrees C and 100 degrees C was identified by the evidence of the grown grain across the bonding interface. In addition, a creep assisted bonding mechanism for the Cu-Cu direct bonding is proposed. Moreover, a shear test was applied on the bonded joints for the investigation of the bonded joint strength and its fracture mode. The mean value of joint strength is 176 MPa which is significantly higher than the conventional solder joint. In summary, the Cu-to-Cu direct bonding by (111) oriented nt-Cu in no-vacuum ambient as well as the grain evolution across the bonding interface has been achieved and verified.
MULTICHANNEL PLANAR MICROELECTRODE ARRAY FOR SOMATIC MAPPING IN RATS
(2011-12-01)
Shaw, Fu-Zen
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Yang, Tsung-Fu
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Huang, Chien-Chun
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Yeh, Keng-Hung
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Chang, Tao-Chih
Planar electrode array is an important tool to evaluate perceptual or cognitive functions of the cortex and prosthetic applications. Many construction methods have been developed. To maximize the usefulness of an array electrode, a low-cost, precise, and flexible microelectrode array with low man power and short construction duration is crucial. In this study, we introduced an 8 x 8 microelectrode array on a flexible polyimide film through microelectronics fabrication. The array dimension was capable of covering the primary somatosensory cortex of a rat. The microelectrode array was insulated with biocompatible Parylene-C except of microelectrode tip. Each electrode tip was 66 mu m height and separated with 0.5 mm to refine a detail somatic sensory processing. In pentobarbital anesthetized rats, stable spontaneous brain activity was successfully recorded through the electrode array. In addition, positive peaks of somatosensory evoked potentials (SEPs) elicited by stimulating rat's whisker pad, forepaw, hindpaw, and tail were obviously and consistently recorded. Latencies of SEPs increased as caudal part of the body was stimulated. The SEPs from stimulation of 4 body parts revealed different spatiotemporal patterns, which indicated a somatotopic organization of the rat. Our results demonstrated the superiority of the planar microelectrode array on the application of simultaneous recording and analysis of the brain activity in rats.
Process Development and Material Characteristics of TSV-less Interconnection Technology for FOWLP
(2017-01-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Chang, Hsiang-Hung
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Kuo, Tzu-Ying
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Fu, Huan-Chun
Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface of RDL and carrier wafer is used for the separation of the reconfigured wafer and carrier wafer with laser de-bonding technology. Since release layer material is the key factor for de-bonding, these materials are evaluated to determine the quality. Test chips are flip-chip bonded onto a carrier wafer with 2 layers of RDL and passivation, following by wafer molding process. Wafers reveal a warp surface due to chemical material shrinkage and CTE mismatch during post mold curing. Warpage of molded wafer is needed to be optimized for equipment handling and the warpage characterization is collected to analyze by different processes. To examine the quality of the structure, electrical measurement is carried out and their respective results are presented.
The investigation of interfacial and crystallographic observation in the Ni(V)/SAC/OSP Cu solder joints with high and low silver content during thermal cycling test
(2015-12-01)
Lee, Christine Jill
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Chen, Wei-Yu
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Chou, Tzu-Ting
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Lee, Tae-Kyu
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Wu, Yew-Chung
This study investigated the microstructure and grain orientation of Ni(V)/SAC396/OSP Cu and Ni(V)/SAC105/OSP Cu solder joints during thermal cycling test (TCT). In general, adjusting Ag content in solders influenced the performance of thermal cycling (TC). Nevertheless, it is still crucial to find the optimal condition of Ag and related mechanisms of crack formation during TCT. This study applied FE-SEM to observe the crack propagation and the precipitation of Sn-Ag IMCs in the solders. Moreover, FE-EPMA and EBSD were used to detect the elemental distribution and grain orientation near the cracks, respectively. The locations of crack initiation are strongly related to the CTE mismatch between Si chip and solder alloy. Besides, the large number of Ag3Sn precipitations in the joint with high Ag content efficiently hinder the crack propagation due to the effects of precipitation hardening. It is revealed that the Ni(V)/SAC396/OSP Cu exhibits good thermal stability during thermal cycle test.
Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology
(2018-08-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Wu, Sheng-Tsai
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Lee, Chia-Hsin
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Huang, Shin-Yi
In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.