Browsing by Author "Chang, Teng-Hung"

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A 2.5-V 14-bit, 180-mW cascaded Sigma Delta ADC for ADSL2+ application
(2007-11-01)
Chang, Teng-Hung
;
Dung, Lan-Rong
;
Guo, Jwin-Yen
;
Yang, Kai-Jiun
;
電控工程研究所
This paper presents a sigma-delta (Sigma Delta) analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application. The core of the ADC is a cascaded 2-1-1 Sigma Delta modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2-MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25 mu tm CMOS technology, in a 2.8 mm(2) active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.
Fourth-Order Cascaded Sigma Delta Modulator Using Tri-Level Quantization and Bandpass Noise Shaping for Broadband Telecommunication Applications
(2008-07-01)
Chang, Teng-Hung
;
Dung, Lan-Rong
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a 14-bit cascaded sigma-delta modulator for broadband telecommunication applications. The modulator is a 2-1-1 cascaded architecture that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.5-MHz signal bandwidth, the modulator achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio of 78.5 dB with an oversampling ratio of 16. The proposed modulator including reference voltage buffers and bandgap circuitry dissipates 62.5 mW from a 2.5-V supply. The active area is 1.2-mm(2) in a 0.25-mu m CMOS technology.