Browsing by Author "Chang, Tian-Sheuan"

Now showing 1 - 20 of 82

135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder
(2013-04-01)
Li, Gwo-Long
;
Chen, Tzu-Yu
;
Shen, Meng-Wei
;
Wen, Meng-Hsun
;
Chang, Tian-Sheuan
To satisfy the video application diversities, an extension of H.264/advanced video coding (AVC), called scalable video coding (SVC), is designed to provide multiple demanded video data via a single video encoder. However, constructed on the fundamental of H.264/AVC, the complexity of SVC is much higher than that of H.264/AVC. In this paper, a VLSI design for all-intra scalable video encoder is proposed to aim at efficient scalable video encoding. First, the memory bandwidth requirements for several encoding methods are analyzed to find out the best encoding method which can achieve best tradeoff between internal memory usage and external memory access. Afterward, an all-intra SVC encoder combined with several advanced techniques, including fast intra prediction algorithm, efficient syntax element encoding approach in context-adaptive variable-length coding, and hardware-efficient techniques, are implemented in a macroblock (MB)-level pipeline to increase data throughput. Implementation results demonstrate that our proposed SVC encoder can process more than 594-k MBs per second, which is equivalent to the summation of 60 high-definition, 1080-p, SD 480-p, and common intermediate format frames under 135-MHz working frequency. The proposed design consumes 258-K gate counts when synthesized by 90-nm CMOS technology.
A 124 Mpixels/s VLSI Design for Histogram-Based Joint Bilateral Filtering
(2011-11-01)
Tseng, Yu-Cheng
;
Hsu, Po-Hsiung
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an efficient and scalable design for histogram-based bilateral filtering (BF) and joint BF (JBF) by memory reduction methods and architecture design techniques to solve the problems of high memory cost, high computational complexity, high bandwidth, and large range table. The presented memory reduction methods exploit the progressive computing characteristics to reduce the memory cost to 0.003%-0.020%, as compared with the original approach. Furthermore, the architecture design techniques adopt range domain parallelism and take advantage of the computing order and the numerical properties to solve the complexity, bandwidth, and range-table problems. The example design with a 90-nm complementary metal-oxide-semiconductor process can deliver the throughput to 124 Mpixels/s with 356-K gate counts and 23-KB on-chip memory.
A 1280x720 pixels 30Frames/s H.264/MPEG-4 AVC intra encoder
(2006)
Cheng, Chao-Chung
;
Ku, Chun-Wei
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an HDTV size H.264/MPEG-4 AVC intra encoder suitable for DSC and digital video camera applications. The chip reduces the gate count by saving the costly plane mode and enhances the video quality with the improved cost function. With careful scheduling and high performance function unit, the developed chip can easily support 29.46M pixels/s still image encoding and real-time moving picture intra coding of HDTV 720p@30fps video application when clocked at 117.28MHz under 0.18um CMOS process.
A 135 MHz 542 k Gates High Throughput H.264/AVC Scalable High Profile Decoder
(2012-04-01)
Li, Gwo-Long
;
Chen, Yu-Chen
;
Liao, Yuan-Hsin
;
Hsu, Po-Yuan
;
Wen, Meng-Hsun
To satisfy the requirement of application heterogeneities, the latest H.264/AVC based video coding standard called scalable video coding additional includes temporal, SNR, and spatial scalabilities for frame rate, quality, and frame resolution adaptation. However, these inclusions significantly increase chip design difficulties such as decoding time, memory bandwidth, and area cost. This paper presents an H.264/AVC scalable high profile decoder realization with several optimization techniques to provide high throughput video decoding. For decoding flow, this paper proposes an one-pass macroblock-based quality layer decoding flow for SNR scalability and 71% of external memory bandwidth and 66% of macroblock processing cycles can be saved. For texture padding in interlayer intra prediction, the modified padding flow can save 26% of decoding time. For interlayer predictor design, this paper proposes a centralized concept for accumulation-based calculation of corresponding spatial position, simplified poly-phase interpolator, and efficient motion vector generator to save area cost and decoding time. Furthermore, the residual reconstruction path with the parallelpipeline architecture is also proposed to cope with the additional decoding complexity and thus leads to 54% of gate count savings compared to the traditional serial-pipeline architecture. Finally, the proposed H. 264/AVC scalable high profile decoder design is implemented with 90 nm CMOS technology and it costs 542 k gate count and 39.66 Kbytes on-chip memory while is capable to decode 60 frames/s for CIF+SD480p+HD1080p resolution with three quality layers at 135 MHz operating frequency.
A 242mW, 10mm(2) 1080p H.264/AVC high profile encoder chip
(2008)
Lin, Yu-Kun
;
Li, De-Wei
;
Lin, Chia-Chun
;
Kuo, Tzu-Yun
;
Wu, Sian-Jin
A 1080p high profile H.264 encoder is designed by the robust reusable silicon IP methodology and fabricated in a 0.13 mu m CMOS technology with an area of 10 mm(2) and 242mW at 145MHz. Compared to the state-of-the-art design targeted at 720p baseline, this design reduces 53.4% power and 46.7% area through parallelism enhanced throughput and cross stage sharing pipeline.
A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video
(2012-11-01)
Liao, Yuan-Hsin
;
Li, Gwo-Long
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based adaptive variable length coding (CAVLC) decoder with 21% shorter critical path delay in comparison to the traditional two-level decoder design. Furthermore, redundant decoding processes are removed by a skipping mechanism. The proposed CAVLC decoder only needs 127.13 cycles per macroblock on average to support level 5.1 decoding with 13.54 k gate counts under 90-nm CMOS technology.
A 61 MHz 72K gates 1280x720 30FPS H.264 intra encoder
(2007)
Li, De-Wei
;
Ku, Chun-Wei
;
Cheng, Chao-Chung
;
Lin, Yu-Kun
;
Chang, Tian-Sheuan
This paper presents an HD720p 30 frames per see H.264 intra encoder operated at 61MHz with just 72K gate count. We achieve the low cost and low operating frequency with the highly utilized variable pixel scheduling, and a modified three-step fast algorithm. Thus, the resulted design only needs half of operating frequency and reduces 30% of area cost compared to the previous HD720p intra encoder design.
A bandwidth efficient subsampling-based block matching architecture for motion estimation
(2005)
Chin, Hao-Yun
;
Cheng, Chao-Chung
;
Lin, Yu-Kun
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
We have developed a new pel subsampling-based search hardware for motion estimation called quartet-pel motion estimation (QME). The memory access of search range memory can be reduced to 25%. The computational complexity can also be reduced to 25% with respect to full-search block matching algorithm (FBMA). On the other hand, flexible and efficient hardware architecture is also implemented. The flexibility is based on the configuration of processing unit, and adjustable candidate number. In addition, complete veimundon and testing methods are also considered.
A display order oriented scalable video decoder
(2006)
Huang, Jia-Bin
;
Lin, Yu-Kun
;
Chang, Tian-Sheuan
;
交大名義發表
;
National Chiao Tung University
As network technologies advance, Scalable Video Coding (SVC) has become increasingly popular due to its universal multimedia access capability and competitive compression performance with the state-of-the-art single-layer video coding. However, it's decoding delay, memory bandwidth and storage requirement are much larger than those of single-layer video coding due to various scalabilities. In this paper, we propose a novel display order instead of direct bitstream order oriented decoding method for the SVC decoder to solve above implementation problems. The analysis for hardware-oriented algorithm shows that the proposed decoding order can reduce the decoding delay, memory bandwidth and storage requirement significantly while is still applicable to various scalable requirements.
A fast algorithm and its architecture for motion estimation in MPEG-4 AVC/H.264 video coding
(2006)
Lin, Chia-Chun
;
Lin, Yu-Kun
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The paper presents a hardware friendly fast algorithm and its architecture for motion estimation (ME) in H.264 video coding. The fast algorithm adopts the quarter pel subsampling and mode filtering that reduces the computing complexity of integer ME by 75%, and only two modes instead of various modes are refined for fractional ME. This also can save about 80% fractional ME cycle counts in average. The simulation result shows that it only increases the bit rate within 2% and at most 0.14dB quality degradation. Finally, the resulted parallel architecture only costs 58% of area cost and requires 48% of cycle counts when compared with the previous designs.
A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding
(2007-05-01)
Wang, Yu-Jen
;
Cheng, Chao-Chung
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a fast algorithm and its VLSI architecture for H.264 fractional motion estimation. Motivated by the high correlation of cost between neighboring fractional pel position, the proposed algorithm efficiently explores the neighborhood position around the minimum one and thus skips other unlikely ones. Thus, the proposed search pattern and early termination under constant quantization parameter can reduce about 50% of computation complexity compared to that in reference software but only with 0.1-0.2 dB peak signal-to-noise ratio degradation and less than 2% of bit rate increase. The VLSI architecture of the proposed algorithm thus can save 40% of area cost due to only half of the processing elements and save 14% of searching time when compared with the previous design.
A fast fractional pel motion estimation algorithm for H.264/MPEG-4 AVC
(2006)
Wang, Yu-Jen
;
Cheng, Chao-Chung
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a fast algorithm for H.264 fractional ME. Motivated by the highly correlation of cost between neighboring fractional pel position, the proposed algorithm efficiently explores the neighborhood position around the minimum one and thus skips other unlikely ones. Thus, the proposed algorithm can complete the search by only examining 8 or 9 search points instead of 17 search points in the search algorithm of reference software. Early termination technique is applied in every single search point The simulation result shows that the proposed algorithm can reduce about 50% of computation complexity compared to that in reference software but only with 0.1-0.2 dB PSNR degradation and less than 2% of bit rate increase.
A Hardware-Efficient Deblocking Filter Design for HEVC
(2015)
Fang, Chih-Chung
;
Chen, I-Wen
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a hardware-efficient deblocking filter architecture for High Efficiency Video Coding (HEVC) to reduce visual artifacts at block boundaries. This design proposes an interleaved scheduling to reduce the intermediate data storage to be 1536 bits instead of whole 8192 bits. The implementation with 90 nm CMOS technology can support real-time deblocking operation of 7682x4320@30 fps under 141.5 MHz with only 31K gate count.
A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video
(2008-07-01)
Lin, Yu-Kun
;
Lin, Chia-Chun
;
Kuo, Tzu-Yun
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
Motion estimation (ME) in high-definition H.264 video coding presents a significant design challenge for memory bandwidth, latency, and cost because of its large search range and various modes. To conquer this problem, this paper presents a low-latency and hardware-efficient ME design with three design techniques. The first technique on integer-pel ME (IME) adopts parallel instead of serial multiresolution search so that we can process 1080 p @ 60 fps videos with +/- 128 search range within just 256 cycles, 5.95-KB buffers, and 213.7K gates. The second technique on fractional-pel ME (FME) uses a single-iteration six-point search to reduce the cycle count by half with similar gate count and negligible quality loss. The third technique applies a mode-filtering approach to further reduce the bandwidth and cycles and share the buffer of IME and FME. The final ME implementation with 0.13-mu m process can support processing of 1080 p @ 60 fps with just 128.8 MHz, 282.6 K gates, and 8.54-KB buffer, which saves 60% gate count, and 68.9% SRAM buffers when compared with the previous design.
A High Throughput CAVLC Design For HEVC
(2012)
Chen, Hsuan-ku
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a high throughput context adaptive variable length coding (CAVLC) hardware design for high bit rate HEVC standard. The proposed design adopts a multi-coefficient encoding architecture with the input-parallel information-cascade method to solve the data dependency while attain high throughput. The final implementation with 90nm CMOS technology can process at least 3.2 coefficients per cycle with 12193 gate count when operate at 270MHz. This processing rate can support real video coding with 4Kx2K@60fps at the high bit rate case.
A High Throughput VLSI Design with Hybrid Memory Architecture for H.264/AVC CABAC Decoder
(2010)
Liao, Yuan-Hsin
;
Li, Gwo-Long
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A high throughput context-based adaptive binary arithmetic coding (CABAC) decoding design with hybrid memory architecture for H.264/AVC is presented in this paper. To accelerate the decoding speed with hardware cost consideration, a new hybrid memory two-symbol parallel decoding technique is proposed. In addition, an efficient mathematical transform method is also proposed to further decrease the critical path of two-symbol binary arithmetic decoding procedure. The proposed architecture is implemented by UMC 90nm technology and experimental results show that our proposal can operate at 264 MHz with 42.37k gate count, and the throughput is 483.1 Mbins/sec, which surpasses previous design with 48.6% hardware cost saving.
A high-definition H.264/AVC intra-frame codec IP for digital video and still camera applications
(2006-08-01)
Ku, Chun-Wei
;
Cheng, Chao-Chung
;
Yu, Guo-Shiuan
;
Tsai, Min-Chi
;
Chang, Tian-Sheuan
This paper presents a real-time high-definition 720p@30fps H.264/MPEG-4 AVC intra-frame codec IP suitable for digital video and digital still camera applications. The whole design is optimized in both the algorithm and architecture levels. In the algorithm level, we propose to remove the area-costly plane mode, and enhance the cost function to reduce hardware cost and to increase the processing speed while provide nearly the same quality. In the architecture design, in additional to the fast module implementation the process is arranged in the macroblock-level pipelining style together with three careful scheduling techniques to avoid the idle cycles and improve the data throughput. The whole codec design only needs 103 K gate count for a core size of 1.28 x 1.28 mm(2) and achieves real-time encoding and decoding at 117 and 25.5 MHz, respectively, when implemented by 0.18-mu m CMOS technology.
A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder
(2012-02-01)
Liao, Yuan-Hsin
;
Li, Gwo-Long
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a high throughput context-based adaptive binary arithmetic coding decoder design is proposed. This decoder employs a syntax element prediction method to solve pipeline hazard problems. It also uses a new hybrid memory two-symbol parallel decoding in order to enhance performance as well as to reduce costs. The critical path delay of the two-symbol binary arithmetic decoding engine is improved by 28% with an efficient mathematical transform. Experimental results show that the throughput of our proposed design can reach 485.76 Mbins/s in the high bit-rate coding and 446.2 Mbins/s on average at 264MHz operating frequency, which is sufficient to support H.264/AVC level 5.1 real-time decoding.
A Low Complexity Speech Coder for Binaural Communication in Hearing Aids
(2012)
Hsu, Shuo-Wen
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a low complexity speech coder with the adaptive Minimum-Maximum Scalar Quantization(MMSQ) method suitable for binaural communication in hearing aids. Compared to the fixed rate MMSQ, the adaptive MMSQ can achieve similar or better compression ratio with 13dB SNR improvement. The final codec implementation with 0.18um CMOS process only costs 6K gate count with 118uW power consumption.
A LOW COST CONTEXT ADAPTIVE ARITHMETIC CODER FOR H.264/MPEG-4 AVC VIDEO CODING
(2007)
Chen, Iian-Long
;
Lin, Yu-Kun
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a fast and low cost context adaptive binary arithmetic encoder for H.264/MPEG-4 AVC video coding standard through both algorithm level and architecture level optimizations. First in the algorithm level, we process the binarization and context generation in parallel to reduce the encoding iteration cycles to three or four cycles from five cycles in the previous design. Second, in the architecture level, we reduce the cycles of renormalization loops by employing one-skipping and bit-parallelism, and save hardware cost of arithmetic coder by merging three different modes. The implemented design shows that it can achieve the 333MHz frequency with only 13.3K gate count.