Browsing by Author "Chang, Tien-Shun"

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Characterization of Enhanced Stress Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering
(2011-04-01)
Lu, Tsung-Yi
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Chang, Tien-Shun
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Huang, Shih-An
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Chao, Tien-Sheng
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電子物理學系
To extend a carrier mobility improvement by strain engineering in high-density and small-gate-space complementary metal-oxide-semiconductor (CMOS) circuits, we have proposed a new stress memorization technique (SMT) that uses a strain proximity free technique (SPFT) to demonstrate the mobility improvement through multiple strain-gate engineering. The electron mobility of n-channel metal-oxide-semiconductor (MOS) field-effect transistors with the SPFT exhibits a 14% increase over counterpart techniques. Compared with the conventional SMT, the SPFT avoids the limitation of the stressor volume for the performance improvement in high-density CMOS circuits. We also found that the preamorphous layer (PAL) gate structure in combination with the SPFT can improve the mobility further to 31% greater than standard devices. Moreover, an additional 30% mobility enhancement can be achieved by using a dynamic threshold-voltage MOS and combining the PAL gate structure with the SPFT, respectively. The gate-oxide reliability and the channel-hot-carrier reliability are also analyzed. Our results show a mobility improvement by the SPFT, a slightly increased gate leakage current, and degraded channel-hot-carrier reliability.
High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique
(2017-02)
Hsieh, Dong-Ru
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Kuo, Po-Yi
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Lin, Jer-Yi
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Chen, Yi-Hsuan
;
Chang, Tien-Shun
In this paper, strained channel-sidewall damascened tri-gate polycrystalline silicon thin-film transistors (SC-SWDTG TFTs) have been successfully fabricated and then demonstrated by an innovative process flow. This process flow without the use of advanced lithography processes combines the sidewall damascened technique (SWDT) and two strain techniques, namely, the strain proximity free technique (SPFT), and the stress memorization technique (SMT), in the poly-Si channels. It has some advantages: (1) the channel shapes and dimensions can be effectively controlled by the wet etching processes and the deposition thickness of the tetraethoxysilane (TEOS) oxide; (2) the source/drain (S/D) resistance can be significantly decreased by the formation of the raised S/D structures; (3) the SPFT, SMT, and the rapid thermal annealing (RTA) treatment can enhance the performance of the SC-SWDTG TFTs without the limitation of the highly scaling stress liner thickness in deep-submicron TFTs. Thus, the SC-SWDTG TFTs exhibit a steep subthreshold swing (S.S.) similar to 110mV/dec., an extremely small drain induced barrier lowing (DIBL) similar to 12.2mVV(-1), and a high on/off ratio similar to 10(7) (V-D = 1V) without plasma treatments for future three-dimensional integrated circuits (3D ICs) applications.
Impacts of Multiple Strain-Gate Engineering on a Zero-Temperature-Coefficient Point
(2013-04-01)
Chang, Tien-Shun
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Lu, Tsung Yi
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Chao, Tien-Sheng
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交大名義發表
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National Chiao Tung University
The impacts of zero-temperature-coefficient (ZTC) points of various strained devices is presented in this letter. The current and mobility are reduced at high temperature by phonon scattering. The degree of mobility reduction becomes severe on devices with multiple strain-gate engineering. The reduction of mobility becomes severe as a result of impurity scattering, which results from gate implantation impurities. The ZTC point is decreased by multiple strain-gate engineering due to the decreased Vth.
Low-Temperature Polycrystalline-Silicon Tunneling Thin-Film Transistors With MILC
(2013-08-01)
Chen, Yi-Hsuan
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Yen, Li-Chen
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Chang, Tien-Shun
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Chiang, Tsung-Yu
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Kuo, Po-Yi
It is known that metal-induced lateral crystallization (MILC) thin-film transistors (TFTs) exhibit higher on-state current, steeper subthreshold slope, and lower minimum leakage than solid-phase-crystallization TFTs. In this letter, we propose a tunneling TFT (T-TFT) fabricated by MILC method for the first time. The MILC T-TFTs demonstrate a lower subthreshold swing, similar to 232 mV/decade, than the other T-TFTs and a high ON/OFF ratio > 10(6) at V-DS = 1 V without any hydrogen-related plasma treatment. These improvements can be due to the reduction of defects at grain boundaries and the channel direction parallel to grains. The polycrystalline silicon T-TFTs fabricated in this letter show a great promise for low standby power circuits, drivers of active-matrix liquid crystal displays, and 3-D integrated circuits applications in the future.
Temperature Dependence of Electron Mobility on Strained nMOSFETs Fabricated by Strain-Gate Engineering
(2012-07-01)
Chang, Tien-Shun
;
Lu, Tsung Yi
;
Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
An effective electron mobility improvement that uses strain-proximity-free technique (SPFT) has been demonstrated using strain-gate engineering. The electron mobility of nMOSFETs with SPFT exhibits a 15% increase over that of counterpart techniques. The preamorphous layer (PAL) gate structure on the SPFT showed a further performance boost. The electron mobility exhibits a 52% improvement in nMOSFET using a combination of SPFT and PAL gate structure. Furthermore, the gain in electron mobility in the SPFT in combination with PAL gate structure decreases at high temperatures. Gate dielectric interface states and ionized gate impurities inducing carrier scattering will play important roles when operating devices under high-temperature conditions.