Browsing by Author "Chang, Wen-Hsiang"

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Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique
(2016)
Chang, Wen-Hsiang
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Chen, Li-De
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Lin, Chien-Hsueh
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Mu, Szu-Pang
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Chao, Mango C. -T.
As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and EM constraints. This paper presents a design flow to generate a PDN that can result in minimal overhead for the routing of the underlying standard cells while satisfying both IR-drop and EM constraints based on a given cell placement. The design flow relies on a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration in order to speed up the search process. The experimental results based on various 28nm industrial block designs have demonstrated the accuracy of the learned model for predicting the routing cost and the effectiveness of the proposed framework for reducing the routing cost of the final PDN.
Generating Routing-Driven Power Distribution Networks With Machine-Learning Technique
(2017-08-01)
Chang, Wen-Hsiang
;
Lin, Chien-Hsueh
;
Mu, Szu-Pang
;
Chen, Li-De
;
Tsai, Cheng-Hong
As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and electromigration (EM) constraints. This paper presents a design flow to generate a PDN that can result in near-minimal overhead for the routing of the underlying standard cells while satisfying both IR-drop and EM constraints based on a given cell placement. The design flow relies on a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration in order to speed up the search process. The experimental results based on various 28 nm industrial block designs have demonstrated the accuracy of the learned model for predicting the routing cost and the effectiveness of the proposed framework for reducing the routing cost of the final PDN.
Mask versus Schematic - An Enhanced Design-Verification Flow for First Silicon Success
(2010)
Luo, Tseng-Chin
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Leong, Eric
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Chao, Mango C-T
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Fisher, Philip A.
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Chang, Wen-Hsiang
Layout versus Schematic (LVS) is a commonly used technique employed at the design stage to insure the correctness of physical layout. However, as process technologies continually advance, increasingly complex boolean operations are required to produce the desired on-mask patterns, which are frequently optimized to enhance transistor performance and process margin. Design layout which has been verified by LVS may undergo substantial layout changes when subjected to the mask generation booleans, with potential implications for performance and margin estimation, particularly given the aggressive use of stressors in modern CMOS technologies. Errors in mask generation booleans, which are very difficult to detect by present primitive inspection methods, can easily result in functional failure although the initial LVS predicted success. Therefore, LVS performed at the design stage is no longer an iron-clad guarantee of chip functionality in advanced process technologies. In this paper, we introduce Mask-versus-Schematic (MVS) verification, a novel design verification flow which directly compares the schematic netlist with a netlist extracted after application of all mask generation booleans, in order to insure the correctness of the final mask data just before tapeout. Furthermore, the introduced methodology can be performed using currently available physical verification EDA tools. The experimental results presented here, using examples from some of the industry\'s most advanced process technology nodes, demonstrate the effectiveness and efficiency of this methodology in detecting errors resulting from mask generation boolean operations.
Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer
(2014-05-01)
Chang, Wen-Hsiang
;
Chao, Mango C. -T.
;
Chen, Shi-Hao
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a novel framework to efficiently and effectively build a robust but routing-friendly multilayer power network under the IR-drop and electro-migration (EM) constraints. The proposed framework first considers the impact of the aluminum-pad layer and provides a conservative analytical model to determine the total metal width for each power layer that can meet the IR-drop and EM constraints. Then the proposed framework can identify an optimal irredundant stripe width by considering the number of occupied routing tracks and the potential routing detour caused by the power stripes without the information of cell placement. Next, after the cell placement is done, the proposed framework applies a dynamic-programming approach to further reduce the potential routing detour by relocating the power stripes. A series of experiments are conducted based on a 40 nm, 1.1 V, and 900-MHz microprocessor to validate the effectiveness and efficiency of the proposed framework.
Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer
(2014-05-01)
Chang, Wen-Hsiang
;
Chao, Mango C. -T.
;
Chen, Shi-Hao
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a novel framework to efficiently and effectively build a robust but routing-friendly multilayer power network under the IR-drop and electro-migration (EM) constraints. The proposed framework first considers the impact of the aluminum-pad layer and provides a conservative analytical model to determine the total metal width for each power layer that can meet the IR-drop and EM constraints. Then the proposed framework can identify an optimal irredundant stripe width by considering the number of occupied routing tracks and the potential routing detour caused by the power stripes without the information of cell placement. Next, after the cell placement is done, the proposed framework applies a dynamic-programming approach to further reduce the potential routing detour by relocating the power stripes. A series of experiments are conducted based on a 40 nm, 1.1 V, and 900-MHz microprocessor to validate the effectiveness and efficiency of the proposed framework.
Predicting Vt Variation and Static IR Drop of Ring Oscillators Using Model-Fitting Techniques
(2017-01-01)
Huang, Tzu-Hsuan
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Hung, Wei-Tse
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Yang, Hao-Yu
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Chang, Wen-Hsiang
;
Chen, Ying-Yen
This paper presents a statistical model-fitting framework to efficiently decompose the impact of device Vt variation and power-network IR drop from the measured ring-oscillator frequencies without adding any extra circuitry to the original ring oscillators. The framework applies Gaussian process regression as its core model-fitting technique and stepwise regression as a preprocess to select significant predictor features. The experiments conducted based on the SPICE simulation of an industrial 28nm technology demonstrate that our framework can simultaneously predict the NMOS Vt, PMOS Vt and static IR drop of the ring oscillators based on their frequencies measured at different external supply voltages. The final resulting R squares of the predicted features are all more than 99.93%.
Statistical Methodology to Identify Optimal Placement of On-Chip Process Monitors for Predicting Fmax
(2016)
Mu, Szu-Pang
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Chang, Wen-Hsiang
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Chao, Mango C. -T.
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Wang, Yi-Ming
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Chang, Ming-Tung
In previous literatures, many approaches use ring oscillators or other process monitors to correlate the chip\'s maximum operating frequency (F-max). But none of them focus on the placement of these on-chip process monitors (OPMs) on a chip. The placement will greatly influence the accuracy of a prediction model. In this paper, we first propose a simulation, framework to sample a chip\'s F-max and it\'s OPM result, These samples are used to develop our methodology of OPM placement and to verify the effectiveness of an OPM placement. Then, a model-fitting framework is presented to correlate the OPMs\' result to chip\'s F-max. Finally, we propose a methodology to idenify optimal placement of OPM for predicting F-max. The experiments demonstrate the effectiveness of our methodology in both simulation and silicon data.
Testing Retention Flip-flops in Power-gated Designs
(2013)
Hsu, Hao-Wen
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Kuo, Shih-Hua
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Chang, Wen-Hsiang
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Chen, Shi-Hao
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Chang, Ming-Tung
This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V-DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-V-DD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.