Browsing by Author "Chang, Wen-Tung"

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A thick CESL stressed ultra-small (Lg=40nm) SiGe-channel MOSFET fabricated with 193nm scanner lithography and TEOS hard mask etching
(2007-01-01)
Liao, Wen-Shiang
;
Chen, Tung-Hung
;
Lin, Hsin-Hung
;
Chang, Wen-Tung
;
材料科學與工程學系
A 100 angstrom-thick SiGe (22.5%) channel MOSFET with gate length down to 40nm has been successfully integrated with 14 angstrom nitrided gate oxide as well as a 1200 angstrom high-compressive PECVD ILD-SiNx stressing layer as the contact etching stop layer (CESL) that enhances the PMOS electron mobility with +33% current gain. To achieve a poly-Si gate length target of 400 angstrom (40nm), a 193nm scanner lithography and an aggressive oxide hard mask etching techniques were used. First, a 500 angstrom-thick TEOS hard mask layer was deposited upon the 1500 angstrom A-thick poly-Si gate electrode. Second, both 1050 angstrom-thick bottom anti-reflective coating (BARC) and 2650 angstrom-thick photoresist (P/R) were coated and a 193nm scanner lithography tool was used for the gate layout patterning with nominal logic 90nm exposure energy. Then, a deep sub-micron plasma etcher was used for an aggressive P/R and BARC trimming down processing and the TEOS hard mask was subsequently plasma etched in another etching chamber without breaking the plasma etcher's vacuum. Continuously, the P/R and BARC were removed with a plasma ashing and RCA cleaning. Moreover, the patterned Si-fin capping oxide can be further trimmed down with a diluted HF(aq) solution (DHF) while rendering the RCA cleaning process and the remained TEOS hard mask is still thick enough for the subsequent poly-Si gate main etching. Finally, an ultra narrow poly-Si gate length of 40nm with promising PMOS drive current enhancement can be formed through a second poly-Si etching, which is above the underneath SiGe (22.5%) conduction channel as well as its upper 14 angstrom-thick nitrided gate oxide.
A thin FinFET Si-fin body structure fabricated with 193nm scanner photolithography and composite hard mask etching technique upon bulk-Si substrate
(2007-01-01)
Liao, Wen-Shiang
;
Liu, Yu-Huan
;
Chang, Wen-Tung
;
Chen, Tung-Hung
;
Shih, Tommy
A thin FinFET bulk Si-fin body structure has been successfully fabricated upon bulk-Si wafers through using 193nm scanner lithography and a composite hard mask etching technique. First, a 100 angstrom-thick buffer SiO2 layer was thermally grown upon the bulk silicon layer and subsequently a 1200 angstrom-thick SiNx layer and a 1000 angstrom-thick TEOS SiO2 hard mask layer was chemically vapor deposited to form a composite hard mask structure of buffer-SiO2/SiNx/TEOS. Second, both 1050 angstrom-thick BARC and 2650 angstrom-thick photoresist (P/R) were coated and a 193nm scanner lithography tool was used for the Si-fin body layout patterning under relatively high exposure energy. This achieves the ADI (after develop inspection) of 80nm from the original as-drawn Si-fin layout of 110nm. Then, a deep sub-micron plasma etcher was used for an aggressive P/R and BARC trimming down processing and both the capping TEOS and CVD-SiNx with its underlying buffer oxide layers were subsequently etched in other etching plasma chambers, respectively. Resultantly, the AMI (after mask inspection) can reach 60nm. Subsequently, both the P/R and BARC were removed with a nominal plasma ashing as well as a RCA cleaning for the final sub-micron Si-fin plasma etching. Eventually, a 60nm-width and 400nm-height bulk Si-fin body structure can be successfully etched out after a fixed time-mode silicon plasma etching.
Advance static random access memory soft fall analysis using nanoprobing and junction delineation transmission electron microscopy
(2007-01-01)
Chang, Wen-Tung
;
Hsieh, Tsung-Eong
;
Zimmermann, Gunnar
;
Wang, Lars
;
材料科學與工程學系
Nanoprobing was used to analyze the soft cell failure of submicron static random access memory (SRAM) at cell level by means of a Zyvex S 100 nanomanipulator system inside a scanning electron microscopy and a multiprobe atomic force probe system, respectively. For the 256 Kbyte dual-port SRAM block, the failure areas exhibit very weak positive-channel field effect transistor drain currents of several magnitudes below the target values, while the drain currents of negative-channel field effect transistor cell transistors are in the expected range. A junction delineation or junction stain was applied to transmission electron microscopy samples to delineate areas with different doping levels so as to make the fail sites visible. Due to the difference in etching behavior of the fail and a reference area, missing lightly doped drain extensions and a partially blocked source/drain implantation were identified as the failure mechanisms. (c) 2007 American Vacuum Society.
Conceptual innovation of a prosthetic hand using TRIZ
(2008-04-01)
Chang, Wen-Tung
;
Tseng, Ching-Huan
;
Wu, Long-Long
;
機械工程學系
;
Department of Mechanical Engineering
Planar linkages with one degree of freedom have been applied to prosthetic hands in the past years, but only one gripping configuration can be performed by these designs. This paper demonstrates the conceptual design processes for a patented prosthetic hand, which has the functions for switching the gripping forms and locking the gripping configuration. A systematically innovative methodology called the Theory of Inventive Problem Solving (TRIZ) is employed to generate the concepts for the desired functions. The skills of Contradiction and Substance-Field Analysis in TRIZ are effectively applied in this study. Also, motion simulation for an embodiment of the proposed prosthetic hand is given by using the Working Model 3D software. The simulating results show that the design is applicable to perform two different gripping forms for hand prostheses.
Dual-metal-gate-integration complementary metal oxide semiconductor process scheme using Ru positive-channel metal oxide semiconductor and TaC negative-channel metal oxide semiconductor gate electrodes
(2007-07-01)
Chang, Wen-Tung
;
Hsieh, Tsung-Eong
;
Lee, Chung-Ju
;
材料科學與工程學系
;
Department of Materials Science and Engineering
This article presents the development of a wet removal process on the integration of complementary metal oxide semiconductor (CMOS) dual metals with Ru for positive-channel metal oxide semiconductor and TaC for negative-channel metal oxide semiconductor on high-k HfO2 gate dielectric. The integration scheme focused on the wet etching capability for the first metal and the selectivity control on the high-k dielectrics under the metal gate. Using the developed chemical, ceric ammonium nitrate and nitric acid mixture used for Ru metal removal and HfO2 treated with Ar/O-2 plasma by selective diluted hydrofluoric wet etching, a CMOS dual-metal-gate structure was achieved with satisfactory device fabrication. (c) 2007 American Vacuum Society.