Browsing by Author "Chang, Win-Ming"

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2.45GHz/5.2GHz switched dual-band CMOS LNA with 4 gain control modes
(2005)
Chang, Win-Ming
;
Cheng, Kuo-Hua
;
Jou, Christina F.
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傳播研究所
;
Institute of Communication Studies
A switched dual-band low noise amplifier with four gain control modes operating at the 2.45-GHz/5.2GHz has been simulated based on a 0.18-um TSMC CMOS process. This dual-band LNA with two input channels and each tuned to 2.45GHz and 5.2GHz separately, by switching the output resonator inductor on/off, the input transistors are enabled/disabled for band selection. A novel gain control scheme is introduced, and this gain control scheme is low in circuit complexity. The four gain control modes are executed by turning on/off the four shunted NMOS at the output of this cascode topology, and the four gain modes can be controlled digitally to adapt to the received RF signals. Compared with the current literatures, this novel gain control scheme not only have high gain control range in both bands, but also have reasonable noise figure in the low gain mode even with 12-dB power gain lower than the high gain mode. The P1dB of the proposed LNA in the low gain mode is 13dB higher than the one in the high gain mode in both bands. The peak of the input and output return loss is locked in band in each gain mode which is an important feature of this proposed LNA. In the high gain mode, the LNA approaches 22-dB maximum power gain and 2.67 DSB noise figure at 2.45GHz. In the 5.2-GHz band, the maximum power gain is 15-dB and the DSB noise figure is 2.47-dB. The gain can be switched by 12-dB between the high gain and the low gain mode at 2.45-GHz and 5.2-GHz.
A dual-band concurrent RF front-end receiver design for GPS and Bluetooth applications
(2005)
Chen, Po-Da
;
Chen, Cheng-Hung
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Chang, Win-Ming
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Cheng, Kuo-Hua
;
Jou, Christina F.
This paper presents a new concurrent dual-band radio frequency receiver front-end design that is intended for Globe Positioning System (GPS) and Bluetooth applications. A low IF architecture is chosen for low-cost and low-power purpose. Using a dual-band sub-harmonic mixer make this new concurrent dual-band receiver architecture requires only a single frequency synthesizer in order the chip area could be reduced. This concurrent frequency synthesizer only needs to provide 0.784GHz and 1.24GHz local frequency signals in this dual-band topology. This receiver is operated at 1.8V, and the simulation shows a voltage gain of 27.7dB at 1.57GHz and 24.2dB at 2.45GHz, a noise figure of 4.13dB at 1.57GHz and 6.84dB at 2.45GHz with a total power consumption of 22.2mW.
A new low voltage CMOS micromixer for 2.45GHz applications
(2006)
Yen, Chin-Hsien
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Chang, Win-Ming
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Cheng, Kuo-Hua
;
Jou, Christina F.
;
傳播研究所
This paper presents a new low voltage CMOS micromixer for 2.45GHz applications, which operates at 1V supply voltage. The new low voltage CMOS micromixer topology modified from basic BJT micromixer uses coupling capacitors to feed the RF signal so as to bias the two transistors in RF stage separately with lower voltage. The charge injection method is also adopted to improve the conversion gain and linearity under low voltage operation. With a power consumption of 1.72 mW the measurement shows voltage gain of 8.28 dB, input 1dB compression point of -5.63 dBm and input third-order intercept point of 4.21 dBm.
A New Sub-harmonic Mixer Using Switched Gm Technique For 802.11a/b/g Dual-Band Receivers
(2007)
Chang, Win-Ming
;
Wu, Hui-I
;
Jou, Christina F.
;
電信工程研究所
;
Institute of Communications Engineering
A new prototype of sub-harmonic mixer using switched Gm technique is designed and implemented in a standard 0.18um CMOS technology. By using the PMOS active load and a switched Gm prototype at LO port, the new sub-harmonic mixer can achieve high conversion power gain and still maintain high linearity, and we can alleviate the shortage of the voltage headroom at IF output. In addition, it consumes no DC power while there is no LO input. At 5.2-GHz ISM band, this fully integrated sub-harmonic mixer achieves measured high conversion power gain of 12.8dB, -1.8dBm input third order intercept point (IIP3), and 14.0dB noise figure at 10-MHz with 4dBm LO power.
Ka-band 0.18 mu m CMOS low noise amplifier with 5.2 dB noise figure
(2007-05-01)
Chang, Win-Ming
;
Hsiung, Zi-Hao
;
Jou, Christina F.
;
電信工程研究所
;
Institute of Communications Engineering
A Ka-band low noise amplifier (LNA) using three cascaded stages was designed and implemented in a standard 0.18 Pun CMOS technology. The fabricated Ka-band LNA achieves power gain (S21) above 12 dB from 30 to 32 GHz and a minimal noise figure of 5.2 dB at 31.5 GHz. The three cascaded stages LNA consume 15.58 mA from I V power supply. Compared with the recent published literatures, this LNA operates at the highest frequency ever reported by standard bulk 0.18 mu m CMOS process. (c) 2007 Wiley Periodicals, Inc.