Browsing by Author "Chang, Y"

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A novel two-step annealing technique for the fabrication of high performance low temperature poly-Si TFTs
(2003-08-01)
Fan, CL
;
Chen, MC
;
Chang, Y
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Low temperature processed (LTP) poly-Si thin film transistors (TFTs) fabricated with a poly-Si film crystallized by a novel two-step annealing (NTSA) technique were investigated and compared with those using conventional solid phase crystallization (SPC) and excimer laser annealing (ELA) schemes. The NTSA scheme is characterized by the combination of an excimer laser induced formation of nucleation centers and a short-time low temperature furnace annealing (about 6 h at 600degreesC) creating clear crystalline grains with very few in-grain defects. The LTP poly-Si TFTs fabricated with a NTSA poly- Si film not only exhibit a better performance but also significantly shorten the crystallization time as compared to those fabricated using the conventional SPC (about 20 h or longer at 600degreesC). In addition, the uniformity of the device characteristics for the devices using the NTSA scheme is superior to that using the ELA scheme and is comparable to that using the SPC scheme. (C) 2003 The Electrochemical Society.
A numerical study of dc characteristics of HEMT with p-type delta-doped barrier
(2005-09-01)
Chang, Y
;
Kuo, YK
;
材料科學與工程學系
;
Department of Materials Science and Engineering
The dc characteristics of an InGaP/InGaAs/GaAs pseudomorphic high-electron-mobility transistor (HEMT) with a p-type delta-doped InGaP barrier are numerically investigated with the ISE-TCAD simulation program. The simulation results indicate that a HEMT with such a structure has a higher gate turn-on voltage, better carrier confinement that results in a lower voltage-dependent transconductance, and a larger breakdown voltage when compared with the typical HEMT. The simulation results also suggest that this structure is beneficial for linear and large-signal application.
Low-temperature-processed polycrystalline silicon thin-film transistors using a new two-step crystallization technique
(2003-10-01)
Fan, CL
;
Chen, MC
;
Chang, Y
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Low-temperature-processed (LTP) Polycrystalline silicon thin-film transistors (poly-Si TFTs) fabricated with a poly-Si film crystallized by a new two-step crystallization (NTSC) technique were investigated. The NTSC is characterized by the combination of excimer-laser-induced formation of nucleation centers and short-time low- temperature furnace annealing to create clear crystalline grains with very few in-grain defects. The LTP poly-Si TFTs fabricated with a NTSC poly-Si film not only exhibit better performance but also significantly shorten the crystallization time (about 6 h at 600degreesC) as compared to those fabricated using conventional solid phase crystallization (about 20 h or longer at 600degreesC).
Modeling finger number dependence on RF noise to 10 GHz in 0.13 mu m node MOSFETs with 80nm gate length
(2004)
King, MC
;
Lai, ZM
;
Huang, CH
;
Lee, CF
;
Ma, MW
We have modeled the as-measured and de-embedded NFmin on multi-fingers 0.13 mum node MOSFETs. In contrast to the as-measured large NFmin value and strong dependence on parallel gate fingers, the de-embedded NFmin. has much smaller noise of only 1.1-1.2 dB for 6, 18 and 36 fingers and weak dependence. From the well calibrated equivalent circuit model with as-measured NFmin, the dominant noise source is from the probing pad generated thermal noise. From our derived equation with excellent agreement with de-embedded NFmin to 10 GHz, the weak dependence of intrinsic NFmin on gate finger is due to the combined effect of R(g)g(m) and drain hot carrier noise but both have weak dependence on finger numbers.
Selective growth of carbon nanotube on scanning probe tips by microwave plasma chemical vapor deposition
(2004-01-01)
Pan, FM
;
Liu, YB
;
Chang, Y
;
Chen, CY
;
Tsai, TG
We have selectively grown carbon nanotubes on the probe tip of an atomic force microscope by microwave plasma chemical vapor deposition. The catalyst domain was defined on the tip apex of an Si based scanning probe by local electric field induced oxidation of a TiN cap layer, under which the cobalt catalyst layer was predeposited on the probe surface. High resolution atomic force microscopy images of an SiO2 trench pattern are demonstrated using the carbon nanotube tip. The nanotube tip fabrication method is simple and compatible with existing thin film process technology. (C) 2004 American Vacuum Society.