Browsing by Author "Chang, Y. W."

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4-GHz fully monolithic SiGe HBT QVCO using superharmonic coupling topology
(2006)
Tseng, S. C.
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Meng, C. C.
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Chang, Y. W.
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Huang, G. W.
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電信工程研究所
This paper demonstrates a 4-GHz monolithic SiGe heterojunction bipolar transistor (HBT) quadrature voltage controlled oscillator (QVCO) using superharmonic coupling topology. The quadrature VCO at 4.17 GHz has phase noise of -116 dBc/Hz at lMHz offset frequency, output power of -6 dBm and the figure of merit (FOM) -179 dBc/Hz. The core current consumption is 3.2 mA at 3V supply voltage. The die size is about 1.4 mm. x 1.2 mm.
4-GHz low-phase-noise transformer-based top-series GaInP/GaAs HBT QVCO
(2006)
Meng, C. C.
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Tseng, S. C.
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Chang, Y. W.
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Su, J. Y.
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Huang, G. W.
The fully integrated GaInP/GaAs heterojunction bipolar transistor (HBT) transformer-based top-series quadrature voltage controlled oscillator (QVCO) is demonstrated at 4 GHz. The transformers on the semi-insulating GaAs substrate possess good electrical properties at high frequencies. The quadrature VCO at 4.1 GHz has phase noise of -120 dBc/Hz at 1MHz offset frequency, output power of 2 dBm and the figure of merit (FOM) -178 dBc/Hz.
9.5 GHz GaInP/GaAs HBT divide-by-two frequency divider using super-dynamic D-type flip-flop technique
(2007-06-21)
Wei, H.-J.
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Meng, C.
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Chang, Y. W.
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Huang, G.-W
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電信工程研究所
A frequency divider with super-dynamic D-type flip-flop is demonstrated in 2 mu m GaInP/GaAs HBT (f(T) = 40 GHz) technology. By biasing the HBT devices around the peak transit-time frequency (f(T)), the operating frequency of a D-FT with ECNFP (emitter-coupled negative feedback pairs) can be improved. At a supply voltage of 5 V a divide-by-two function of 9.5 GHz is achieved.
Analysis of bump resistance and current distribution of ultra-fine-pitch microbumps
(2013-01-01)
Chang, Y. W.
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Peng, H. Y.
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Yang, R. W.
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Chen, Chih
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Chang, T. C.
To keep up with the demand of continuous increase in device densities, the integration of three-dimensional integrated circuits (3D-IC) has become the most probable solution, and the utilization of ultra-fine-pitch microbump has emerged as an essential component of 3D-IC technology. In this study, a Kelvin bump structure was fabricated and resistances measured at different angles on a 20.0 mu m microbump were investigated. The microbump resistance at 0 degrees, 60 degrees, 120 degrees, and 180 degrees are 74.7, 45.9, 14.6, and 13.7 m Omega, respectively. These high resistances in microbumps may result in high interconnect resistance and cause resistance/capacitance (RC) delay, and thus lower the electrical performance of 3D-IC. A series of finite-element-model (FEM) was built to analyze the distribution of electric field in microbump. The FEM results have shown that the current is distributed uniformly in the thin solder joint, but current crowding still occurs in the Cu under-bump-metallization (UBM). The finding of the current crowding in the Cu UBM is the main cause of high resistances in the microbump. Thickening the Al trace, for example, from 0.4 mu m to 1.5 mu m, is a direct solution to reduce the unexpected high microbump resistance. A numerical model which treated solder joints as a resistance network was also performed in this study. For comparison, both FEM and the numerical model show the same trend and agree with the measurement results from Kelvin bump structure. The results all point to one thing: thickening the Al trace turn out to be the most effective approach to reduce high microbump resistance. When the Al trace thickness is increased from 0.8 to 3.0 mu m, the microbump resistance is decreased to half of the original value, resulted from the alleviation of current crowding in the Cu UBM. (C) 2012 Elsevier Ltd. All rights reserved.
C-band fully integrated SiGe HBT superharmonic QVCO
(2007-04-01)
Tseng, S. C.
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Meng, C. C.
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Chang, Y. W.
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Huang, G. W.
;
電信工程研究所
This paper demonstrates a 4-GHz monolithic SiGe heterojunction bipolar transistor quadrature voltage-con trolled oscillator (QVCO) using superharmonic coupling topology. The QVCO at 4.17 GHz has phase noise of -116 dBc/Hz at 1 MHz offset frequency, output power of -6 dBm, and the figure of merit - 179 dBc/Hz. The core current consumption is 3.2 mA at 3 V supply voltage. The die size is about 1.4 mm X 1.2 mm. (c) 2007 Wiley Periodicals. Inc.
Characterization and Monte Carlo analysis of secondary electrons induced program disturb in a buried diffusion bit-line SONOS flash memory
(2007)
Tang, Chun-Jung
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Li, C. W.
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Wang, Tahui
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Gu, S. H.
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Chen, P. C.
A new program disturb in a buried diffusion bit-line SONOS array is observed as a bit-line width is reduced. A multi-step Monte Carlo simulation is performed to explore the disturb mechanism. We find that the V, shift of a disturbed cell is attributed to impact ionization-generated secondary electrons in a neighboring cell when it is in programming. The effects of substrate bias, bit-line dimension and pocket implant on the program disturb are characterized and evaluated by a Monte Carlo simulation.
Effect of migration and condensation of pre-existing voids on increase in bump resistance of flip chips on flexible substrates during electromigration
(2008-07-01)
Liang, S. W.
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Chang, Y. W.
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Chen, Chih
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Preciado, Jackie
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Tu, K. N.
In Pb-free solder joints formed by reflowing a bump of solder paste, voids are formed within the solder due to the residue of flux in the reflow process. These voids migrate toward the cathode contact during electromigration under current stressing. Accompanying the electromigration, resistance jumps of a few 100 m Omega were observed. It was postulated that a jump occurs when a void touches the cathode contact. This study investigated the effect of the void migration and condensation on the change in bump resistance using three-dimensional (3D) simulations and finite element analysis. It was found that there was negligible change in bump resistance during void migration towards the high-current-density region before touching the cathode contact opening. When a small void condensed on the contact opening and depleted 18.4% of the area, the bump resistance increased only 0.4 m Omega. Even when a large void depleted 81.6% of the opening, the increase in bump resistance was 3.3 m Omega. These values are approximately two orders of magnitude smaller than those reported in the literature for the change in resistance due to void migration in flip chips on flexible substrates. We conclude that the reported change in resistance was most likely that of the Al or Cu interconnection in the flip-chip samples.
Effect of Si-die dimensions on electromigration failure time of flip-chip solder joints
(2011-05-16)
Chang, Y. W.
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Chiu, S. H.
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Chen, Chih
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Yao, D. J.
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材料科學與工程學系
Electromigration tests were performed for solder joints with various Si dies thickness and area. For the electro-migration in flip-chip solder joints with a 60, 100.250 and 760 mu m thick Si die, it is found that Si-die thickness has profound influence on electro-migration lifetime. The average failure time was 1608.0 h for joints with a 760-mu m-thick die when they are stressed by 1.0 A at 100 degrees C. However, it decreased significantly to 0.6 h for joints with a 60-mu m-thick die. According to the temperature measured by infrared microscopy, solder joints with a thinner die has a higher Joule heating effect, which results in a shorter electromigration lifetime. In addition, the die area has a considerable influence on the electromigration failure time. The electromigration failure time decreases as the die area decreases. The average failure time is 1608.0,28.0, 10.6,5.0 and 0.3 h for the solder joints with die area of 5350 x 4350 mu m(2), 5350 x 3600 mu m(2), 5350 x 3000 mu m(2), 5350 x 2000 mu m(2) and 5350 x 1000 mu m(2), respectively. The Joule heating effect becomes more serious in smaller dies, which causes a shorter electromigration lifetime. (C) 2011 Elsevier B.V. All rights reserved.
Effect of three-dimensional current and temperature distributions on void formation and propagation in flip-chip solder joints during electromigration
(2006-07-10)
Liang, S. W.
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Chang, Y. W.
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Shao, T. L.
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Chen, Chih
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Tu, K. N.
Effect of three-dimensional current distribution on void formation in flip-chip solder joints during electromigration was investigated using thermoelectrical coupled modeling, in which the current and temperature redistributions were coupled and simulated at different stages of void growth. Simulation results show that a thin underbump metallization of low resistance in the periphery of the solder joint can serve as a conducting path, leading to void propagation in the periphery of the low current density region. In addition, the temperature of the solder did not rise significantly until 95% of the contact opening was eclipsed by the propagating void. (c) 2006 American Institute of Physics.
Effect of void propagation on bump resistance due to electromigration in flip-chip solder joints using Kelvin structure
(2007-09-24)
Chang, Y. W.
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Chiang, T. H.
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Chen, Chih
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材料科學與工程學系
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Department of Materials Science and Engineering
Three-dimensional modeling is employed to simulate various Kelvin structures for detecting the change in bump resistance due to void formation and propagation during electromigration in flip-chip solder joints. It is found that the Kelvin structures can sense the highest voltage drop when its voltage probes are placed at the current entrance into the bump on the chip side, and it is thus the most sensitive design to monitor void formation and propagation. When the bump resistance increases 20% of its initial value, the depletion percentage of contact opening ranges from 21.0% to 65.0%, depending on the position of the probes. (c) 2007 American Institute of Physics.
Fast phase transformation due to electromigration of 18 mu m microbumps in three-dimensional integrated-circuit integration
(2014-12-15)
Chang, Y. W.
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Chen, Chih
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Chang, T. C.
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Zhan, C. J.
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Juang, J. Y.
The electromigration behavior was investigated in 18-mu m SnAg microbumps at 150 degrees C. The monitored resistance increase abruptly soon after the current stressing of 4.6 x 10(4) A/cm(2) was applied but the resistance rose much slower after a certain period of time. The formation of the high-resistivity Ni3Sn4 intermetallic compounds (IMCs) was responsible for the abrupt resistance increase in the beginning of the current stressing. The whole solder joint was transformed into an IMC joint. Because IMC has a higher electromigration resistance than the solder, a much slower increase in resistance was resulted after the solder joint was transformed into IMCs. (C) 2014 Elsevier B.V. All rights reserved.
Geometrical effect of bump resistance for flip-clip solder joints: Finite-element modeling and experimental results
(2006-08-01)
Liang, S. W.
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Chang, Y. W.
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Chen, Chih
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Liu, Y. C.
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Chen, K. H.
The bump resistance of flip-chip solder joints was measured experimentally and analyzed by the finite-element method. Kelvin structures for flip-chip solder joints were designed and fabricated to measure the bump resistance. The measured value was only about 0.9 m Omega at room temperature, which was much lower than that expected. Three-dimensional (3-D) modeling was performed to examine the current and voltage distribution in the joint. The simulated value was 7.7 m Omega, which was about 9 times larger than the experimental value. The current crowding effect was found to be responsible for the difference in bump resistance. Therefore, the measured bump resistance strongly depended on the layout of the Kelvin structure. Various layouts were simulated to investigate the geometrical effect of bump resistance, and a significant geometrical effect was found. A proper layout was proposed to measure the bump resistance correctly. The Kelvin structure would play an important role in monitoring void formation and microstructure changes during the electromigration of flip-chip solder joints.
Hot-Carrier Injection-Induced Disturb and Improvement Methods in 3D NAND Flash Memory
(2019-01-01)
Lin, Wei-Liang
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Tsai, Wen-Jer
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Cheng, C. C.
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Lu, Chun-Chang
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Ku, S. H.
We investigate a hot-carrier injection- induced program disturb in a 3D NAND flash memory. As there exist specific coding patterns, a "down-coupling" region and a "pre-charge" regions are formed during program-verify and the following program phases, respectively, in the inhibit cell strings. A high heating field is built nearby the PGM wordline. Hot carriers may inject into the inhibit cells as Vpgm is applied. Soft ramp-down and pre-turn-on schemes are proposed to mitigate this disturb.
Investigation of Void Nucleation and Propagation in the Joule Heating Effect During Electromigration in Flip-Chip Solder Joints
(2010-11-01)
Chang, Y. W.
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Chiu, S. H.
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Chen, Chih
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材料科學與工程學系
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Department of Materials Science and Engineering
This study analyzes the effect of void propagation on the temperature increase of solder joints by using x-ray microscopy, Kelvin probes, and infrared microscopy. It was found that the temperature rise due to void formation was less than 1.3 degrees C when the voids depleted about 75% of the contact opening, even though bump resistance had increased to 10.40 times its initial value. However, the temperature rose abruptly with an increase of up to 8.0 degrees C when the voids depleted 96.2% of the contact opening. A hot spot was observed immediately before the occurrence of open failure in the solder bump. The local increase in temperature was about 30.2 degrees C at the spot. This spot may be the remaining contact area immediately before the occurrence of open failure.
Low-phase-noise transformer-based top-series QVCO using GaInP/GaAs HBT technology
(2007-01-01)
Meng, C. C.
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Tseng, S. C.
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Chang, Y. W.
;
Su, J. Y.
;
Huang, G. W.
The fully integrated GaInP/GaAs heterojunction bipolar transistor, transformer-based top-series quadrature voltage controlled oscillator (QVCO) is demonstrated at 4 GHz. The transformers on the semi-insulating GaAs substrate possess good electrical properties at high frequencies. The QVCO at 4.1 GHz has phase noise of - 120 dBc/Hz at 1 MHz offset frequency, output power of 2 dBm and the figure of merit -178 dBc/Hz. (c) 2006 Wiley Periodicals, Inc.
Optimal Design of Passivation/UBM Openings for Reducing Current Crowding Effect Under Electromigration of Flip-chip Solder Joint
(2009)
Chang, Y. W.
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Chen, Chih
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材料科學與工程學系
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Department of Materials Science and Engineering
Electromigration of flip-chip solder joints has been studied extensively in recent years. It was investigated in plenty of studies that the current crowding effect takes place at the corner near the traces due to huge differences of dimensions between traces and solder joint. The local high current density, which has been known as a serious reliability issue, causes the failure such as void formation and under bump metallization (UBM) consumption to occur much earlier than expected in the current-crowding region in solder bump. As a result, to relieve the current crowding effect can significantly increase the mean-time-to-failure (MTTF) of solder bump, since the MTTF may be doubled when the local current density is reduced to half of its original value. However, there is still no technology can observe the current density directly in a current stressed sample. In order to obtain more precise observation, a three-dimensional finite element model (3D-FEM) was performed to simulate the current density distribution in solder bump. Several dimensions, radius of Al pad, passivation opening and width of Al trace, in this model were varied to analyze the current density distribution. The UBM opening is 60 mu m. The width of Al trace, the radius of Al pad and the passivation opening were varied from 50 mu m to 100 mu m by 10 mu m, 60 mu m to 120 mu m by 10 mu m, and 12 mu m to 48 mu m by 3 mu m respectively. The most effective design to relieve the current crowding effect which was found in this study is to fix the ratio of the radius of passivation opening and UBM opening between 0.5 to 0.6. The ratio is relative to the width of Al trace and the radius of Al pad. The ratio is close to 0.6 with a larger radius of Al pad and a narrower Al trace. On one hand, the ability of relieving current crowding effect is only relative to the radius of passivation opening when the ratio is less than 0.3. On the other hand, the ability of relieving current crowding effect is also limited by the radius of the Al pad. The wider the Al trace is, the lower the current crowding will be. When the radius of Al pad is larger than 100 mu m, the change of Al trace width makes no influence on relieving current crowding effect. The influence of these dimensions, width of Al trace, radius of Al pad and passivation opening show saturated condition. This approach facilitates the systemic study of optimized design to relieve the current crowding effect and thus increase the EM resistance of solder joints. In addition, the results provide a guideline for optimal design for solder joints with a specific UBM structure.
Poly-Silicon Trap Position and Pass Voltage Effects on RTN Amplitude in a Vertical NAND Flash Cell String
(2016-08)
Chou, Y. L.
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Wang, Tahui
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Lin, Mercator
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Chang, Y. W.
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Liu, Lenvis
We investigate the dependence of random telegraph noise (RTN) on a poly-silicon trap position in a 3D vertical channel and charge-trapping NAND flash cell string. We characterize RTN in read current of each cell of a string at different read and pass voltages. RTN characteristics resulting from a trap in a read cell or in a pass cell are differentiated. A method to identify a poly-silicon trap position in a NAND string is proposed. We perform the 3D TCAD simulation to calculate channel electron density in a string. Measured RTN characteristics can be explained by current-path percolation and channel carrier screening effects. The distribution of RTN amplitudes in NAND strings is characterized.
Relieving hot-spot temperature during electromigration in solder and current crowding effects bumps by using Cu columns
(2007-10-01)
Liang, S. W.
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Chang, Y. W.
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Chen, Chih
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材料科學與工程學系
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Department of Materials Science and Engineering
Solder joints with Cu columns appear to be one of the best structures to resist electromigration. Three-dimensional thermoelectrical analysis was employed to simulate the current density and temperature distributions for eutectic SnPb solder bumps with 0.5, 5, 25, 50, and 100 mu m Cu under bump metallization (UBM). It was found that the hot spots and current crowding effects in the solder were reduced significantly when the Cu thickness was over 50 Pm, whereas the overall Joule heating effect remained almost unchanged. The mechanism by which the Cu column is effective in relieving the hot spot and current crowding effects is to keep the solder away from the heat source and crowding region. Simulated at a current of 0.6 A and 70 degrees C, the estimated mean time to failure of the joints with a 50-mu m-thick Cu column was 6.7 times longer than that of joints with a 0.5-mu m-thick Cu UBM.
Study of electromigration of flip-chip solder joints using Kelvin probes
(2007)
Chang, Y. W.
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Chen, Chih
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材料科學與工程學系
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Department of Materials Science and Engineering
Kelvin bump probes were fabricated in flip-chip solder joints, and they were employed to monitor the void formation during electromigration. We found that voids started to form at approximately 5% of the failure time under 0.8 A at 150 degrees C, and the bump resistance increased only 0.02 m Omega in the initial stage of void formation. Three-dimensional simulation was performed to examine the increase in bump resistance at different stages of void formation, and it fitted the experimental results quite well. This technique provides a systematic way for investigating the void formation during electromigration.
Study of void formation due to electromigration in flip-chip solder joints using Kelvin bump probes
(2006-07-17)
Chang, Y. W.
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Liang, S. W.
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Chen, Chih
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材料科學與工程學系
;
Department of Materials Science and Engineering
Kelvin bump probes were fabricated in flip-chip solder joints, and they were employed to monitor the void formation during electromigration. We found that voids started to form at approximately 5% of the failure time under 0.8 A at 150 degrees C, and the bump resistance increased only 0.02 m Omega in the initial stage of void formation. Three-dimensional simulation was performed to examine the increase in bump resistance at different stages of void formation, and it fitted the experimental results quite well. This technique provides a systematic way for investigating the void formation during electromigration. (c) 2006 American Institute of Physics.