Browsing by Author "Chang, Yeong-Jar"

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On the Design of Power-Rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-Voltage CMOS Process
(2009)
Ker, Ming-Dou
;
Chiu, Po-Yen
;
Tsai, Fu-Yi
;
Chang, Yeong-Jar
;
電子工程學系及電子研究所
A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25 degrees C in the silicon chip. Moreover, it can achieve ESD robustness of over 8kV in human-body-model (HBM) and 750V in machine-model (MM) ESD tests, respectively.
Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process
(2009)
Chiu, Po-Yen
;
Ker, Ming-Dou
;
Tsai, Fu-Yi
;
Chang, Yeong-Jar
;
電子工程學系及電子研究所
A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25 degrees C, which is much smaller than that (613 mu A) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.