Browsing by Author "Chang, You-Tai"

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Characterization of Four-Level Random Telegraph Noise in a Gate-All-Around Poly-Si Nanowire Transistor
(2019-01-01)
Chang, You-Tai
;
Li, Pei-Wen
;
Lin, Horng-Chih
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Four-level random-telegraph-noise (RTN) characteristics of a gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistor induced by two discrete traps are studied in this work. By carefully analyzing the RTN, depths of the two traps in the gate oxide can be identified separately. Consistent information is obtained by assessing the probability of transitions between different levels.
Fabrication and characterization of novel gate-all-around polycrystalline silicon junctionless field-effect transistors with ultrathin horizontal tube-shape channel
(2018-04-01)
Chang, You-Tai
;
Peng, Kang-Ping
;
Li, Pei-Wen
;
Lin, Horng-Chih
;
電機學院
In this paper, we report on a novel fabrication process for the production of junctionless field-effect transistors with an ultrathin polycrystalline silicon (poly-Si) tube channel in a gate-all-around (GAA) configuration. The core of the poly-Si tube channel is filled with either a silicon nitride or a silicon oxide layer, and the effects of the core layers on the device characteristics are evaluated. The devices show excellent switching performance, thanks to the combination of the ultrathin tube channel and the GAA structure. Hysteresis loops in the transfer characteristics of the nitride-core devices are observed, owing to the dynamic trapping of electrons in the nitride core. (C) 2018 The Japan Society of Applied Physics.
Study on random telegraph noise of high-idmetal-gate gate-all-around poly-Si nanowire transistors
(2020-04-01)
Chang, You-Tai
;
Tsai, Yueh-Lin
;
Peng, Kang-Ping
;
Su, Chun-Jung
;
Li, Pei-Wen
In this Paper, we investigated random telegraph noise (RTN) characteristics of gate-all-around poly-Si nanowire (NW) transistors with high-kappa oxide/metal-gate (HK/MG) stack. Distinct two-level RTN signals were measured on NW transistors with effective channel length of 150 nm and channel width of 30 nm. Values of time constants for charge emission from and capture by traps were extracted from measured RTN signals We proposed a new theoretical scheme to evaluate the location and energy level of the corresponding trap. The trap was assessed to be present within the interfacial layer (IL) at a spatial location approximate 1 nm away from the IL/channel interface and 68 nm in proximity to the source side. (C) 2020 The Japan Society of Applied Physics