Browsing by Author "Chang, Yu-Hong"

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1-V Full-Swing Depletion-Load a-In-Ga-Zn-O Inverters for Back-End-of-Line Compatible 3D Integration
(2016-04)
Chi, Li-Jen
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Yu, Ming-Jiue
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Chang, Yu-Hong
;
Hou, Tuo-Hung
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電子工程學系及電子研究所
To enable monolithic three-dimensional integration of the amorphous In-Ga-Zn-O (a-IGZO) and CMOS technologies, the a-IGZO inverters compatible with the low operating voltage (<= 1 V) and process temperature of back-end-of-line CMOS have been investigated. We demonstrated a full-swing depletion-load inverter with a voltage gain up to 24 using a CMOS-compatible operating voltage of 1 V. The drive transistor was realized using a low-voltage enhancement-mode a-IGZO thin-film transistor (TFT) with a steep subthreshold swing of 70 mV/decade and a low threshold voltage of 0.5 V. The load transistor was implemented using a bi-layer a-IGZO channel, where the a-IGZO composition was modulated simply by the oxygen flow rate in a depletion-mode TFT.
Abnormal positive bias stress instability of In-Ga-Zn-O thin-film transistors with low-temperature Al2O3 gate dielectric
(2016-01-18)
Chang, Yu-Hong
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Yu, Ming-Jiue
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Lin, Ruei-Ping
;
Hsu, Chih-Pin
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Hou, Tuo-Hung
Low-temperature atomic layer deposition (ALD) was employed to deposit Al2O3 as a gate dielectric in amorphous In-Ga-Zn-O thin-film transistors fabricated at temperatures below 120 degrees C. The devices exhibited a negligible threshold voltage shift (Delta V-T) during negative bias stress, but a more pronounced Delta V-T under positive bias stress with a characteristic turnaround behavior from a positive Delta V-T to a negative Delta V-T. This abnormal positive bias instability is explained using a two-process model, including both electron trapping and hydrogen release and migration. Electron trapping induces the initial positive Delta V-T, which can be fitted using the stretched exponential function. The breakage of residual AlO-H bonds in low-temperature ALD Al2O3 is triggered by the energetic channel electrons. The hydrogen atoms then diffuse toward the In-Ga-Zn-O channel and induce the negative Delta V-T through electron doping with power-law time dependence. A rapid partial recovery of the negative Delta V-T after stress is also observed during relaxation. (C) 2016 AIP Publishing LLC.
High-Voltage Amorphous InGaZnO TFT With Al2O3 High-k Dielectric for Low-Temperature Monolithic 3-D Integration
(2016-10)
Yu, Ming-Jiue
;
Lin, Ruei-Ping
;
Chang, Yu-Hong
;
Hou, Tuo-Hung
;
電子工程學系及電子研究所
On-chip high-voltage (HV) power management integrated circuits would deliver smaller form factor, lower system cost, higher power efficiency, and suppressed noise in system-on-chip designs. A reliable HV amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology has been presented for potential applications of monolithic 3-D integration on CMOS. By using a process temperature below 200 degrees C, the instability of positive-and negative-bias stresses can be carefully minimized. The HV a-IGZO TFT with an Al2O3 high-k gate dielectric possesses a high breakdown voltage exceeding 45 V, a high saturation mobility of 11.3 cm(2)/Vs, and a large ON-/OFF-current ratio of 10(9). The long-term reliability study projects that the device can be operated at 20 V for ten years without catastrophic dielectric breakdown while maintaining sufficient ON-current.
Reliable High-Voltage Amorphous InGaZnO TFT for Monolithic 3D Integration
(2016)
Yu, Ming-Jiue
;
Lin, Ruei-Ping
;
Chang, Yu-Hong
;
Hou, Tuo-Hung
;
電子工程學系及電子研究所