Browsing by Author "Chang, Yuan-Yao"

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A novel array-based test methodology for local process variation monitoring
(2009)
Luo, Tseng-Chin
;
Chao, Mango C. -T.
;
Wu, Michael S. -Y.
;
Li, Kuo-Tsai
;
Hsia, Chin C.
As process technologies continually advance, local process variation has greatly increased and gradually become one of the most critical factors for IC manufacturing. To monitor local process variation, a large number of DUTs (device-under-test) in close proximity must be measured. In this paper, we presents a novel array-based test structure to characterize local process variation with limited area overhead. The proposed test structure can guarantee high measurement accuracy by utilizing the proposed hardware IR compensation and voltage bias elevation. Furthermore, the DUT layout need not be modified for the proposed test structure so that the measured variation exactly reflects the reality in the manufacturing environment. The measured results from the few most advanced process-technology nodes demonstrate the effectiveness and efficiency of the proposed test structure in quantifying local process variation.
A Novel Array-Based Test Methodology for Local Process Variation Monitoring
(2011-05-01)
Luo, Tseng-Chin
;
Chao, Mango C. -T.
;
Wu, Michael Shien-Yang
;
Li, Kuo-Tsai
;
Hsia, Chin C.
As process technologies continually advance, local process variation has greatly increased and gradually become one of the most critical factors for integrated circuit manufacturing. To monitor local process variation, a large number of devices-under-test (DUTs) in close proximity must be measured. In this paper, we present a novel array-based test structure to characterize local process variation with limited area overhead. The proposed test structure can guarantee high measurement accuracy by application of the test techniques proposed in this paper: hardware IR compensation, voltage bias elevation, and leakage-current cancelation. Furthermore, the DUT layout need not be modified for the proposed test structure. Thus, the measured variation exactly reflects the reality in the manufacturing environment. The measured results from the few most advanced process-technology nodes demonstrate the effectiveness and efficiency of the proposed test structure in quantifying local process variation.
Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization
(2014-05-01)
Luo, Tseng-Chin
;
Chao, Mango C. -T.
;
Tseng, Huan-Chi
;
Goto, Masaharu
;
Fisher, Philip A.
As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layoutdependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (V-t) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, V-t must be measured for a sufficiently large number of device-under- tests (DUTs) to obtain a statistically representative sample population. The number of V-t measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve V-t testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of similar to 2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of V-t = 0.15 mV, versus typical accuracy of similar to 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs. Index Terms-Design for manufacturing (DFM), Threshold
Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization
(2014-05-01)
Luo, Tseng-Chin
;
Chao, Mango C. -T.
;
Tseng, Huan-Chi
;
Goto, Masaharu
;
Fisher, Philip A.
As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layoutdependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (V-t) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, V-t must be measured for a sufficiently large number of device-under- tests (DUTs) to obtain a statistically representative sample population. The number of V-t measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve V-t testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of similar to 2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of V-t = 0.15 mV, versus typical accuracy of similar to 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs. Index Terms-Design for manufacturing (DFM), Threshold
On the Efficiency of Executing Diverse Game Tree Search Applications in a Volunteer Computing Federation
(2013-01-01)
Chen, Lung-Ping
;
Wu, I-Chen
;
Chang, Yuan-Yao
;
Tseng, Wen-Jie
;
資訊工程學系
A game tree search application can be implemented as the malleable parallel jobs that are adapted to various processor allocations. We establish an efficient desktop grid federation to enable the small to mid-sized organizations to perform large-scale game tree search tasks via resource sharing. Due to the uneven task scales of the organizations as well as the dynamic generation/pruning of game tree search tasks, the user credits of the desktop grids may fluctuate dramatically, leading an unstable resource allocation to the hosted applications. This paper shows that stable processor allocation leads to higher efficiency for the parallel tasks. A new brokering algorithm is developed that ensures both fairness and stable resource allocation.