Browsing by Author "Chang Edward Yi"

Now showing 1 - 16 of 16

Current limit circuit apparatus
(2014-05-27)
Chen Tsung-Lin
;
Chang Edward Yi
;
Chieng Wei-Hua
;
Cheng Stone
;
Jeng Shyr-Long
The present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The source and the drain of the first transistor couple with the diode. The source of the second transistor couples with the gate of the first transistor. The source of the first transistor couples with the first transistor. The source of the second transistor couples with the second resistor. The third resistor couples with the fourth resistor and the gate of the first transistor. The first transistor turned off and the gate current is limited. When the current of the gate of the GaN transistor exceeds the predetermined value, the breakdown voltage is increased by limiting the gate current.
High Electron Mobility Transistor and Method for Fabricating the Same
(2011-06-30)
Chang Edward Yi
;
Kuo Chien-I
;
Hsu Heng-Tung
A high electron mobility transistor includes a substrate, a buffer layer, a channel layer, a spacer layer, a schottky layer and a cap layer. The buffer layer is formed on the substrate. The channel layer is formed on the buffer layer, in which the channel layer comprises a superlattice structure formed with a plurality of indium gallium arsenide thin films alternately stacked with a plurality of indium arsenide thin films. The spacer layer is formed on the channel layer. The schottky layer is formed on the spacer layer. The cap layer is formed on the schottky layer.
High electron mobility transistor and method for fabricating the same
(2012-05-01)
Chang Edward Yi
;
Kuo Chien-I
;
Hsu Heng-Tung
A high electron mobility transistor includes a substrate, a buffer layer, a channel layer, a spacer layer, a schottky layer and a cap layer. The buffer layer is formed on the substrate. The channel layer is formed on the buffer layer, in which the channel layer comprises a superlattice structure formed with a plurality of indium gallium arsenide thin films alternately stacked with a plurality of indium arsenide thin films. The spacer layer is formed on the channel layer. The schottky layer is formed on the spacer layer. The cap layer is formed on the schottky layer.
High-side driver circuit
(2013-11-12)
Chen Tsung-Lin
;
Chang Edward Yi
;
Chieng Wei-Hua
;
Cheng Stone
;
Jeng Shyr-Long
The present invention provides a high-side driver circuit including a power transistor, the first transistor, the second transistor, the second capacitor, the second diode, a start-up circuit. The start-up circuit is coupled between a resistor and the second capacitor to complete a gate driving circuit. And, the aforementioned resistor can either be the gate resistance of the power transistor or an external resistor. The design of start-up circuit enables the functionality of the bootstrap capacitor of being charged to a designate voltage level. Thus, the depletion-mode transistor can be controlled to turn on/off without a floating voltage source or a negative voltage source.
III-V metal-oxide-semiconductor device
(2013-08-27)
Chang Edward Yi
;
Lin Yueh-Chin
A hafnium oxide layer, between a III-V semiconductor layer and a metal oxide layer is used to prevent interaction between the III-V semiconductor layer and the metal oxide layer.
Method for forming a GexSi1-x buffer layer of solar-energy battery on a silicon wafer
(2011-10-11)
Chang Edward Yi
;
Tang Shih-Hsuan
;
Lin Yue-Cin
The method is disclosed that Si+ is implanted on Si substrate to enhance strain relaxation at the interface between the metamorphic GexSi1−x buffer layers and Si substrate, in order to facilitate the growth of a high quality Ge on Si substrate. And several GexSi1−x buffer layers (Si/Ge0.8Si0.2/Ge0.9Si0.1/Ge) are grown on top of Si substrate by UHVCVD. Then grow pure Ge layer of low dislocation density on GexSi1−x buffer layer. Finally, grow up high efficiency III-V solar cell on GexSi1−x buffer layer.
Method for forming T-shaped gate structure
(2013-05-07)
Chang Edward Yi
;
Huang Lu-Che
;
Chang Chia-Hua
;
Lin Yueh-Chin
;
Chieng Wei-Hua
A method for forming a T-shaped gate is provided. The method includes providing a substrate. Then, a photoresist structure is formed over the substrate. The photoresist structure includes two development rates. Next, a mask with an opening is formed over the photoresist structure to pattern the photoresist structure. An angle exposure is applied to the photoresist structure, and the exposed photoresist structure is developed to form a T-shaped notch. A width of the T-shaped notch is gradually reduced from a top portion thereof to a bottom portion to expose a surface of the substrate. Then, a gate metal is deposited in the T-shaped notch. Thereafter, the patterned photoresist structure is removed to form the T-shaped gate.
Method for reducing defects in epitaxially grown on the group III-nitride materials
(2011-10-06)
Chang Edward Yi
;
Wong Yuen Yee
The present invention discloses a method to grow group III-nitride materials on a non-native substrate with much reduced threading dislocation (TD) density and smooth surface by using MBE. The first layer is to suppress the formation of screw TD while the second layer is to bend the propagation of edge TD. After that, the migration enhanced epitaxy (MEE) approach is used to smoothen the second layer surface before a main layer of group III-nitride is growth to the thickness required for different applications. All of these steps are performed in the MBE reactor by carefully control over the arrival rate and sequence of group III atoms and nitrogen radicals onto the sample substrate. By using reflective high energy electron diffraction (RHEED), the change of each layer's surface morphology can be monitored during the growth to achieve the high quality group III-nitride materials.
MULTILAYER SUBSTRATE HAVING GALLIUM NITRIDE LAYER AND METHOD FOR FORMING THE SAME
(2012-11-29)
Chang Edward Yi
;
Hsiao Yu-Lin
;
Lu Jung-Chi
The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.
MULTILAYER SUBSTRATE HAVING GALLIUM NITRIDE LAYER AND METHOD FOR FORMING THE SAME
(2012-04-26)
Chang Edward Yi
;
Hsiao Yu-Lin
;
Lu Jung-Chi
The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.
Multilayer substrate having gallium nitride layer and method for forming the same
(2013-09-17)
Chang Edward Yi
;
Hsiao Yu-Lin
;
Lu Jung-Chi
The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.
Multilayer substrate having gallium nitride layer and method for forming the same
(2012-09-11)
Chang Edward Yi
;
Hsiao Yu-Lin
;
Lu Jung-Chi
The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.
Sub-wavelength structure layer, method for fabricating the same and photoelectric conversion device applying the same
(2011-06-23)
Chang Edward Yi
;
Sahoo Kartika Chandra
;
Lin Men-Ku
;
Lu Yi-Yao
;
Wang Sheng-Ping
The present invention relates to a method for fabricating a sub-wavelength structure layer, including: forming a metal film on a passivation layer, an n-GaN layer or a transparent conductive oxide layer; performing thermal treatment to form self assembled metal nano particles; using the metal nano particles as a mask to remove a partial area of the passivation layer, the n-GaN layer or the transparent conductive oxide layer to form a sub-wavelength structure of which the cross-sectional area increases along the thickness direction of the passivation layer, the n-GaN layer or the transparent conductive oxide layer; and removing the metal nano particles. In addition, the present invention further provides the obtained sub-wavelength structure layer and a photoelectric conversion device using the same.
Sun-chasing device
(2014-05-27)
Sie You-Long
;
Chang Edward Yi
;
Jeng Shyr-Long
;
Chieng Wei-Hua
;
Lue Bin-Han
A sun-chasing device is provided, including a base, a first transmitter disposed on the base, a second transmitter, a support, a carrier pivotally connected to the support for carrying a solar module, a first supporting component pivotally connected to the first transmitter and the carrier, and a second supporting component pivotally connected to the second transmitter and the carrier. The sun-chasing device has great rigidity and carrying ability against strong wind, and has great precision and rotation angle, such that a solar plate can precisely aim at sun for long time and thus the efficiency of a solar module is significantly increased.
Vertical transmission line structure that includes bump elements for flip-chip mounting
(2012-05-01)
Chang Edward Yi
;
Wu Wei-Cheng
;
Hwang Ruey-Bing
;
Hsu Li-Han
A vertical transmission structure for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the conductive axial core. The vertical transmission structure is applied to a high-frequency flip chip package for reducing the possibility of underfill from coming in contact with the conductive axial core.
Vertical transmission line structure that includes bump elements for flip-chip mounting
(2011-05-10)
Chang Edward Yi
;
Wu Wei-Cheng
;
Hwang Ruey-Bing
;
Hsu Li-Han
A vertical transmission structure for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the conductive axial core. The vertical transmission structure is applied to a high-frequency flip chip package for reducing the possibility of underfill from coming in contact with the conductive axial core.