Browsing by Author "Chang Hua-Yu"

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Designing an optimal wiring topology for electromigration avoidance
(2013-03-19)
Jiang Hui-Ru
;
Chang Hua-Yu
;
Chang Chih-Long
A method for designing an optimal wiring topology for electromigration avoidance is disclosed. The wiring topology includes multiple sources, multiple sinks and multiple wires. The method includes the following steps: A feasible wire, a wire of the shortest length connecting each pair of source and sink, is calculated, and the capacity of each feasible wire is decided. An initial feasible topology is found. A flow network is created based on the initial topology. Negative cycles are iteratively checked and removed until no more negative cycles.
Method of implementing timing engineering change order
(2014-07-08)
Chang Hua-Yu
;
Jiang Hui-Ru
;
Chang Yao-Wen
A method of implementing timing ECO in a circuit includes the steps of performing a static timing analysis on the circuit so as to determine at least one timing violating path of the circuit, decomposing the timing violating path into at least one violating path segment, determining a smooth curve from each timing violating path and determining a plurality of reference points along the smooth curve, computing a fixability parameter of each gate on the violating path segment, extracting at least one gate according to the fixability parameters, and selecting one spare cell and disposing the selected spare cell on the violating path segment.
METHOD OF IMPLEMENTING TIMING ENGINEERING CHANGE ORDER
(2013-11-07)
Chang Hua-Yu
;
Jiang Hui-Ru
;
Chang Yao-Wen
A method of implementing timing ECO in a circuit includes the steps of performing a static timing analysis on the circuit so as to determine at least one timing violating path of the circuit, decomposing the timing violating path into at least one violating path segment, determining a smooth curve from each timing violating path and determining a plurality of reference points along the smooth curve, computing a fixability parameter of each gate on the violating path segment, extracting at least one gate according to the fixability parameters, and selecting one spare cell and disposing the selected spare cell on the violating path segment.