Browsing by Author "Chang Yao-Jen"

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INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE
(2015-02-05)
Chen Kuan-Neng
;
Chang Yao-Jen
An interconnection structure of a semiconductor device is provided, where the interconnection structure is constructed in a semiconductor substrate. The interconnection structure includes a first through silicon via and a second through silicon via both penetrating the semiconductor substrate, and the first through silicon via is spaced from the second through silicon via by a distance ranged from 2 μm to 40 μm.
Submicron connection layer and method for using the same to connect wafers
(2015-02-10)
Chen Kuan-Neng
;
Chang Yao-Jen
A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.
THREE-DIMENSIONAL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE
(2012-09-13)
Chen Kuan-Neng
;
Chang Yao-Jen
A three-dimensional complementary metal oxide semiconductor device comprises a bottom wafer having a first-type strained MOS transistor; a top wafer stacked on the bottom wafer face to face or face to back, having a second-type strained MOS transistor arranged opposite to the first-type strained MOS transistor, and having a plurality of metal pads and a plurality of TSVs connected to the metal pads; and a hybrid bonding layer arranged between the bottom wafer and the top wafer, having metallic-bonding areas connecting the first-type and second-type MOS transistors to TSVs and a non-metallic bonding area filled in all space except the metallic bonding areas, so as to bond the bottom and top wafers.