Browsing by Author "Chang-Liao, Kuei-Shu"

Now showing 1 - 5 of 5

Advance in next Century nanoCMOSFET research
(2007-10-31)
Hwang, Huey-Liang
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Chiou, Yan-Kai
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Chang, Che-Hao
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Wang, Chen-Chan
;
Lee, Kun-Yu
It is well known that Taiwan's IC industry is in the very leading front of the world, and production of 65 nm devices was launched in 2006. Within a few years, the need of high-k dielectrics and metal gates is eminent and truly indispensable. Professor H.L. Hwang (the author) organized 12 professors and 50 graduate students of National Tsing Hua University and Chiao Tung University, and executed this particular project, which is sponsored by the Ministry of Economic Affairs of Republic of China, and is aimed at treating efficiently this problem and transferred the critical technologies to industry in a time frame of 3 years. (C) 2007 Elsevier B.V. All rights reserved.
Crucial integration of high work-function metal gate and high-k blocking oxide on charge-trapping type flash memory device
(2008-12-22)
Tsai, Ping-Hung
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Chang-Liao, Kuei-Shu
;
Yang, Dong-Wei
;
Chung, Yuan-Bin
;
Wang, Tien-Ko
Charge-trapping type flash memory devices with various integrations of metal gates having different work functions and blocking oxides were investigated in this work. Improved erasing speed together with acceptable reliability characteristics can be achieved by the integration of high work-function metal gate and high-k blocking oxide due to an efficient suppression of electron back tunneling through the blocking oxide during erasing operation for the MoN sample. Specifically, the high work-function value of MoN metal gate can be kept only by integrating with the Al(2)O(3) blocking oxide because it can suppress the formation of molybdenum-silicide. Moreover, high-speed erasing can also be demonstrated by combining the MoN metal gate with an HfAlO charge trapping layer when band-to-band hot hole erasing method is adopted.
National Project on 45 to 32 nm Metal Oxide Semiconductor Field Effect Transistors for Next Century IC Fabrications
(2008)
Hwang, Huey-liang
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Wang, C. W.
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Chang, K. H.
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Tsai, C. H.
;
Leou, K. C.
It is well known that the Taiwan Semiconductor industries play the very key roles for the worldwide IC foundry, and the advanced research of nanoelectronics is the lifeline for its long term developments. Professor Huey-liang Hwang effectively integrated the most outstanding research team and resource in Taiwan on the National Project on Nanometer CMOS Transistors for the 21 century, which is sponsored by the Ministry of Economic Affairs of ROC. A dozen of Professors from NTHU( National Tsing Hua University) with expertise at the novel materials and analysis and NCTU( National Chiao Tung University) with expertise at devices and reliability are devoted to the studies and are in collaboration with the world-wide-known company such as TSMC, and breakthrough of the key technologies of 45-32 nm technologies are achieved. The objective of this project is focused on the development of advanced metal gate/high-k MOSFET for 45 nm node generation and beyond, the efforts include the world first successful suppression the oxide/Si interfacial layer formation by using a bi-layer composite of HfO2 3.2 nm (ALD)/HfO2 1.5 nm (MBE), the results show a dielectric constant of 16 and an EOT of 1.15 nm, a Dit was estimated to be 4.6x10(11)cm(-2)eV(-1) with the leakage at Vfb-1V being 8.5x10(-6) A/cm(2). Also, the thermal stability of HfO2, HfAlOx alloy and Al2O3/HfO2 stack, prepared by ALD were compared, the incorporation of Al in alloy form gave superior characteristics by retaining an amorphous structure up to 1000 C, which suppress the leakage current and retards growth of the interfacial layer giving the least increment of EOT and interface traps. Besides, by incorporating Al into TiO2 gave an EOT value of the Al2O3/TiAlOx/Al2O3 film down to 0.8 nm. Furthermore, high selectivity was obtained via etching the HfAlO and silicon wafer with pattern using the ICP Plasma. In this project, YbSi metal gate for n-MOSFET and IrSi metal gate p-MOSFET were successfully fabricated for the HfAlON MESFET. The results showed the good effective workfunction of 4.15 and 4.9 eV and no degradation of gate dielectric current and mobility in the YbxSi/HfAlON and IrxSi/HfAlON FUSI-gates by reducing the metal diffusion at lower temperatures.
Record-high 121/62 mu A/mu m on-currents 3D stacked epi-like Si FETs with and without metal back gate
(2013)
Yang, Chih-Chao
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Chen, Szu-Hung
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Hsieh, Tung-Ying
A sequential layered integration technology that can fabricate 3D stackable epi-like Si FETs with and without metal back gate (MBG) under sub-400 degrees C are proposed in this article. With laser crystallized epi-like Si and CMP thinning processes for channel fabrication, 3D stackable ultra thin body (UTB) n/p-MOSFETs with low-subthreshold swings (88 and 121 mV/dec.) and high on-currents (121 and 62 liA/Iim) are demonstrated. With additional metal back gate structure, UTB devices can be desirably operated in a positive or negative threshold voltage range with gamma values of 0.51 (n-MOSFETs) and 0.56 (p-MOSFETs) for favoring its applications in 3D logic circuits. In addition, such thin and high quality channel and metal back gate scheme is not only promising for conventional p-n junction device but also junctionless (JL) scheme, which can simplify the fabrication and achieve further scaling.
Using spike-anneal to reduce interfacial layer thickness and leakage current in metal-oxide-semiconductor devices with TaN/Atomic layer deposition-grown HfAlO/chemical oxide/Si structure
(2008-04-01)
Tsai, Bo-An
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Lee, Yao-Jen
;
Peng, Hsin-Yi
;
Tzeng, Pei-Jer
;
Luo, Chih-wei
In this study, the characteristics of Ta/chemical SiO(2)/Si devices with their chemical oxides formed by various chemicals, including HNO(3), SCl, and H(2)SO(4)+H(2)O(2) solutions, were first investigated. We found the HNO(3) split depicts the lowest leakage current and the best hysteresis behavior. Next, chemical oxide formed by HNO(3) was applied to form the interfacial SiO(2) layer for metal-oxide-semiconductor (MOS) devices with Ta/HfAlO/chemical SiO(2)/Si structrue. The effects of a high-temperature spike anneal were then studied. We found that the spike-anneal process can effectively reduce the thickness of the chemical oxide from 10 to 7 angstrom, thus is beneficial in preserving the low effective oxide thickness (EOT) of the structure. Furthermore, both the gate leakage current and stress-induced leakage current (SILC) were also effectively suppressed by the high-temperature spike-anneal.