Browsing by Author "Chao, CJ"

Now showing 1 - 11 of 11

An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits
(2000-05-01)
Wong, SC
;
Lee, TGY
;
Ma, DJ
;
Chao, CJ
;
電子工程學系及電子研究所
We develop an empirical model for the crossover capacitance induced by the wire crossings in VLSI with multilevel metal interconnects. The crossover capacitance, which is formed in any three adjacent layers and of a three-dimensional (3-D) nature, is derived in closed form as a function of the wire geometry parameters. The total capacitance on a wire passing many crossings can then be easily determined by combining the crossover capacitance with the two-dimensional (2-D) intralayer coupling capacitance defined on a same layer. The model agrees well with the numerical field solver (with a 6.7% root-mean-square error) and measurement data (with a maximum error of 4.17%) for wire width and spacing down to 0.16 mu m and wire thickness down to 0.15 mu m. The model is useful for VLSI design and process optimization.
An extraction method to determine interconnect parasitic parameters
(1998-11-01)
Chao, CJ
;
Wong, SC
;
Chen, MJ
;
Liew, BK
;
電子工程學系及電子研究所
Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are destructive (such as SEM measurement) or can determine only partial parasitic parameters (such as large capacitor measurement), In this paper, we present a new method for extracting interconnect parasitic parameters, which can simultaneously determine the interlayer and intralayer capacitances, line resistance, and effective line width. The method is based on two test patterns of a same structure with different dimensions. The structure consumes less wafer area than existing methods. The method shows good agreement with SEM measurement of dielectric thickness in both nonglobal planarized and chemical-mechanical polished processes, and gives accurate prediction of the process spread of a ring oscillator speed over a wafer.
An extraction method to determine interconnect parasitic parameters
(1998-11-01)
Chao, CJ
;
Wong, SC
;
Chen, MJ
;
Liew, BK
;
電子工程學系及電子研究所
Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are destructive (such as SEM measurement) or can determine only partial parasitic parameters (such as large capacitor measurement), In this paper, we present a new method for extracting interconnect parasitic parameters, which can simultaneously determine the interlayer and intralayer capacitances, line resistance, and effective line width. The method is based on two test patterns of a same structure with different dimensions. The structure consumes less wafer area than existing methods. The method shows good agreement with SEM measurement of dielectric thickness in both nonglobal planarized and chemical-mechanical polished processes, and gives accurate prediction of the process spread of a ring oscillator speed over a wafer.
Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product
(2003-08-01)
Lin, IC
;
Huang, CY
;
Chao, CJ
;
Ker, MD
;
電子工程學系及電子研究所
Latchup failure induced by electrostatic discharge (ESD) protection circuits occurred anomalously in a high-voltage IC product. Latchup issues existed at only three output pins, two of which belonged to the top and the other to the side. The layouts of top and bottom output pins are identical, and side output pins have another identical layouts. In our experiments it was found latchup of two top output pins were originated from the latchup of the side output pin, and therefore heat-induced latchup aggravation issue must be noticed during latchup test. Furthermore, large power line current (Idd) existed during triggering this side output pin and led to subsequent latchup. After thorough layout inspection, the layout of this side output pin is identical to all other side output pins except that it has an additional N-well (NW) resistor of gate-triggered high-voltage PMOS beside. It was later proved by engineering experiments that this NW resistor is the origin of inducing latchup in this product, and a new mechanism was proposed for this latchup failure. Improvements and solutions were also provided to successfully solve the latchup issues of these three output pins. (C) 2003 Elsevier Ltd. All rights reserved.
Characterization and Modeling of on-chip inductor substrate coupling effect
(2002)
Chao, CJ
;
Wong, SC
;
Hsu, CJ
;
Chen, MJ
;
Leu, LY
The substrate coupling effects of two adjacent coplanar spiral inductors are characterized and modeled. The noise magnitude between two 45mum-away inductors can be reduced by 6.83 dB by using guard-ring surrounding each inductor, and improved by 10.28 dB further by adding patterned ground polysilicon shield beneath at 3 GHz. The inductor with patterned polysilicon shield beneath shows improved quality factor and noise isolation. Moreover, a macro model is presented for modeling quality factor and inductance of on-chip spiral inductor and associated neighboring inductor's coupling noise effect.
Characterization and modeling of on-chip inductor substrate coupling effect
(2002)
Chao, CJ
;
Wong, SC
;
Hsu, CJ
;
Chen, MJ
;
Leu, LY
The substrate coupling effects of two adjacent coplanar spiral inductors are characterized and modeled. The noise magnitude between two 45mum-away inductors can be reduced by 6.83 dB by using guard-ring surrounding each inductor, and improved by 10.28 dB further by adding patterned ground polysilicon shield beneath at 3 GHz. The inductor with patterned polysilicon shield beneath shows improved quality factor and noise isolation. Moreover, a macro model is presented for modeling quality factor and inductance of on-chip spiral inductor and associated neighboring inductor's coupling noise effect.
Characterization and Modeling of on-chip inductor substrate coupling effect
(2002-01-01)
Chao, CJ
;
Wong, SC
;
Hsu, CJ
;
Chen, MJ
;
Leu, LY
The substrate coupling effects of two adjacent coplanar spiral inductors are characterized and modeled. The noise magnitude between two 45mum-away inductors can be reduced by 6.83 dB by using guard-ring surrounding each inductor, and improved by 10.28 dB further by adding patterned ground polysilicon shield beneath at 3 GHz. The inductor with patterned polysilicon shield beneath shows improved quality factor and noise isolation. Moreover, a macro model is presented for modeling quality factor and inductance of on-chip spiral inductor and associated neighboring inductor's coupling noise effect.
Characterization and Modeling of on-chip spiral inductors for Si RFICs
(2002-02-01)
Chao, CJ
;
Wong, SC
;
Kao, CH
;
Chen, MJ
;
Leu, LY
The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then investigated. It is shown that floating well can improve both quality factor and noise elimination by itself under 3 GHz and together with a guard ring above 3 GHz. Finally, for accurate circuit simulations, a new inductor model is developed for predicting the skin effect and eddy effect and associated quality factor and inductance.
Design optimization of ESD protection and latchup prevention for a serial I/O IC
(2004-02-01)
Huang, CY
;
Chen, WF
;
Chuan, SY
;
Chiu, FC
;
Tseng, JC
ESD/latchup are often two contradicting variables during IC reliability development. Trade-off between the two must be properly adjusted to realize ESD/latchup robustness of IC products. A case study on SERIAL Input/Output (I/O) IC's is reported here to reveal this ESD/latchup optimization issue. SERIAL I/O IC features a special clamping property to wake up PC's during system standby situation. Along with high voltage operation, Input/Output (I/O) protection design of this IC becomes one of the most challenging tasks in the product reliability development. In the initial development phase, ignorance of latchup susceptibility resulted in severe Electrical Overstress (EOS) damage during latchup tests, and also gave a false over estimate of ESD protection threshold through parasitic latchup paths. The latchup origin is an output PMOS and floating-well ESD triggering NMOS beside the PMOS, and the main fatal link is this high-voltage (HV) NMOS connecting to a bi-directional SCR cell. This fatal link led to totally five latchup sites and three latchup paths clarified through careful and intensive FIB failure analysis, while this powerful SCR ESD device without appropriate triggering mechanism still could not provide sufficient product-level ESD hardness. Owing to there being no design window between ESD and latchup, the original several protection schemes were all abandoned. Using this bi-directional SCR ESD cell and proper triggering PNP bipolar transistors, a new I/O protection circuit could sustain at least ESD/HBM 4 kV and latchup triggering current 150 mA tests, thus accomplish the best optimization of ESD/latchup robustness. (C) 2003 Elsevier Ltd. All rights reserved.
Fuzzy pattern recognition model for diagnosing cracks in RC structures
(1998-04-01)
Chao, CJ
;
Cheng, FP
;
土木工程學系
;
Department of Civil Engineering
This paper examines a diagnostic model based on the concept of cause-and-effect diagramming and fuzzy pattern recognition, which contributes a new methodology for diagnosing engineering problems. Three examples are presented to demonstrate the feasibility of the model in diagnosing crack formations in reinforced concrete structures. Two levels of parameters representing the causes of cracks in concrete are used to form fuzzy sets. The parameters represent the materials used, fabrication of structural elements, loading, and environmental conditions. An expert system that links the parameters by means of fuzzy set theory is constructed using finite universal sets consisting of membership functions and fuzzy vectors. Pattern recognition is used to identify a fuzzy vector that represents the most likely causes of the crack.
New insights on RF CMOS stability related to bias, scaling, and temperature
(2000)
Su, JG
;
Wong, SC
;
Chang, CY
;
Chiu, KY
;
Huang, TY
The stability issues of CMOS devices for RF applications were studied. The stability factor of MOS devices based on the small-signal model (SSM) parameters was derived, for the first time. The results reveal some new insights on the effects of biasing, and scaling parameters on the stability; and were subsequently confirmed by our experimental results. Our results also show that unconditional stability of RF CMOS devices can be obtained with proper biasing and device geometries. Finally, the effects of temperature on stability were also: investigated. Our results suggest that careful attention needs to be paid for stable low temperature operation.