Browsing by Author "Chao, CM"

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A compact DSP core with static floating-point arithmetic
(2006-02-01)
Lin, TJ
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Lin, HY
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Chao, CM
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Liu, CW
;
Jen, CW
A multimedia system-on-a-chip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate data-intensive computations. But most of these DSP cores are designed originally for standalone applications, and they must have some overlapped (and redundant) components with the host microprocessor. This paper presents a compact DSP for multi-core systems, which is fully programmable and has been optimized to execute a set of signal processing kernels very efficiently. The DSP core was designed concurrently with its automatic software generator based on high-level synthesis. Moreover, it performs lightweight arithmetic-the static floating-point (SFP), which approximates the quality of floating-point (FP) operations with the hardware similar to that of the integer arithmetic. In our simulations, the compact DSP and its auto-generated software can achieve 3X performance (estimated in cycles) of those DSP cores in the dual-core baseband processors with similar computing resources. Besides, the 16-bit SFP has above 40 dB signal to round-off noise ratio over the IEEE single-precision FP, and it even outperforms the hand-optimized programs based on the 32-bit integer arithmetic. The 24-bit SFP has above 64 dB quality, of which the maximum precision is identical to that of the single-precision FP. Finally, the DSP core has been implemented and fabricated in the UMC 0.18 mu m 1P6M CMOS technology. It can operate at 314.5 MHz while consuming 52mW average power. The core size is only 1.5 mmx1.5 mm including the 16 KB on-chip memory and the AMBA AHB interface.
Code placement and replacement strategies for wideband CDMA OVSF code the management
(2001)
Tseng, YC
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Chao, CM
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Wu, SL
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資訊工程學系
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Department of Computer Science
The use of OVSF codes in WCDMA systems has offered opportunities to provide variable data rates to flexibly support applications with different bandwidth requirements. Two rarely addressed issues on such environment are the code placement problem and code replacement problem. The former may have significant impact on code utilization and thus code blocking probability, while the latter may affect the code reassignment cost if dynamic code. assignment is to be conducted. The general objective is to make the OVSF code tree as compact as possible in order to support new calls, either with less blocking or with less reassignment cost. This paper is perhaps the first one which addresses these issues on WCDMA. Three simple strategies, which can be adopted by both code placement and code replacement, are proposed: random, leftmost, and crowded-first. Among them the crowded-first strategy looks most promising, which is shown to be able to reduce, for example, the code blocking probability by 77 % and the number of reassignments by 81 % as opposed the random strategy when the system is 80% fully loaded and the max SF=256.
Dynamic bandwidth allocation for multimedia traffic with rate guarantee and fair access in WCDMA systems
(2005-09-01)
Chao, CM
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Tseng, YC
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Wang, LC
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資訊工程學系
;
電信工程研究所
Packet scheduling in a WCDMA system poses a new challenge due to its nature of variable bit rates and location-dependent, time-varying channel conditions. In this work, three new downlink scheduling algorithms for a WCDMA base station are proposed to support multimedia transmissions. Using a credit management and a compensation mechanism, our algorithms provide rate guarantee and fair access to mobile terminals. In particular, we propose to allow a user to simultaneously use multiple OVSF codes in a time-sharing manner, which we call a multicode, shared model. Using multiple codes allows us to compensate those users suffering from bad communication quality or even errors. The proposed schemes can tolerate a multistate link condition (compared to the typically assumed two-state, or good-or-bad, link condition) by adjusting the number of OVSF codes and the spreading factor of each code. Simulation results show that the proposed schemes do achieve higher bandwidth utilization while keeping transmission delay low.
Dynamic channel allocation with location awareness for multi-hop mobile ad hoc networks
(2002-05-01)
Tseng, YC
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Chao, CM
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Wu, SL
;
Sheu, JP
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資訊工程學系
The wireless mobile ad hoc network (MANET) has received a lot of attention recently. This paper considers the channel assignment problem in a MANET which has access to multiple channels. Although a MANET does not have the infrastructure of base stations, interestingly its channel assignment can be conducted efficiently in a way very similar to that in cellular systems (such as GSM). In this paper, we propose a new location-aware channel assignment protocol called GRID-B (read as GRID with Channel Borrowing), which is a sequel of our earlier GRID protocol [Location-aware channel assignment for a multi-channel mobile ad hoc network, Technical Report NCU-HSCCL-2000-02, 2000]. The protocol assigns channels to mobile hosts based on the location information of mobile hosts that might be available from the positioning device (such as GPS) attached to each host. According to our knowledge, no location-aware channel assignment protocol has been proposed before for MANETs. Several channel borrowing strategies are proposed to dynamically assign channels to mobile hosts so as to exploit channel reuse and resolve the unbalance of traffic loads among different areas (such as hot and cold spots). We then propose a multi-channel MAC protocol, which integrates GRID-B. Extensive simulation results are presented to show the advantage of the new GRID-B protocol. (C) 2002 Elsevier Science B.V. All rights reserved.
Hierarchical instruction encoding for VLIW digital signal processors
(2005)
Liu, CH
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Lin, TJ
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Chao, CM
;
Hsiao, PC
;
Lin, LC
VLIW-based architectures are very popular in high-performance DSP processors, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixed-length instruction encoding, (2) NOP insertion due to limited parallelism, and (3) repetitive codes for loop unrolling. This paper describes a novel hierarchical instruction encoding that address these three problems to improve the VLIW code density. In our simulations, the proposed encoding scheme saves 61.4%-66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP processor. The prototype is implemented in the 0.18um CMOS technology with its operating frequency at 208MHz.
Lightweight arithmetic units for VLSI digital signal processors
(2005)
Ou, SH
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Lin, TJ
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Lin, HY
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Chao, CM
;
Liu, CW
This paper presents a lightweight arithmetic for embedded signal processing, whose hardware complexity is similar to that of the integer one. In our simulations, its 16-bit version has 40.18dB signal to round-off error ratio over the IEEE single-precision floating-point arithmetic, which even out-performs the hand-optimized 32-bit code with integer arithmetic.
Location awareness in ad hoc wireless mobile networks
(2001-06-01)
Tseng, YC
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Wu, SL
;
Liao, WH
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Chao, CM
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交大名義發表
Networks composed of dynamically repositioning mobile hosts require location awareness to provide new geographic services and to maximize routing efficiency and quality of service.
Novel programmable digital signal processor for multimedia applications
(2004)
Lin, LC
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Lin, TJ
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Lee, CC
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Chao, CM
;
Chen, SK
This paper presents a novel DSP architecture for multimedia applications. The DSP core is a simple RISC processor from the programmer's view, which has a high-performance DSP unit and the applications can be easily targeted on the RISC shell to reduce the development time. Moreover, the DSP unit is itself a fully-programmable 4-way VLIW datapath, which has a novel ping-pong register file. To smooth the instruction execution of the two-level programmable DSP processor and improve the code density, we propose a hierarchical encoding scheme for variable-length instructions. The simulations show that our DSP has comparable performance with state-of-the-art DSP architectures, and the hierarchical instruction encoding saves 31%-64% code sizes compared to the fixed-length instruction encoding.
Reducing internal and external fragmentations of OVSF codes in WCDMA systems with multiple codes
(2005-07-01)
Chao, CM
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Tseng, YC
;
Wang, LC
;
資訊工程學系
;
電信工程研究所
In the third-generation partnership project technical specification, orthogonal variable spreading factor (OVSF) codes are used as channelization codes. The use of OVSF codes can provide variable data. rates,to flexibly support applications with different bandwidth requirements. Most works in the literature assume that only one single OVSF code is used to support one connection. This may sometimes waste the scarce wireless bandwidth since the allocated bandwidth will increase exponentially as the spreading factor decreases, i.e., a user may be "overserved". In this paper, we consider the possibility of using multiple OVSF codes to support a connection. We show how using multiple codes can reduce the internal and external fragmentations of an OVSF code tree. The tradeoff between bandwidth utilization and hardware complexity of a multicode system is analyzed. The result shows that using two or three codes will be quite cost effective. Several multicode assignment and reassignment strategies, namely, random, leftmost, crowded-first-space, and crowded-first-code, are proposed based on such an environment. Our simulation results show significant increase in code tree utilization and significant reduction in code blocking probability by using the crowded-first-space and crowded-first-code schemes.