Browsing by Author "Chao, CP"

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A floating well method for exact capacitance-voltage measurement of nano technology
(2003-06-01)
Su, HD
;
Chiou, BS
;
Wu, SY
;
Chang, MH
;
Lee, KH
Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.
Bi-mode breakdown test methodology of ultrathin oxide
(2003-12-01)
Su, HD
;
Chiou, BS
;
Ko, CY
;
Wu, SY
;
Chang, MH
The breakdown detections of ultrathin oxide (1.4-2 nm) using a fast voltage ramp have been studied. It was found that the breakdown voltage test of deep sub-micron technology requires the reduction of the gate area of test patterns and therefore the increase of the number of structures due to a large inversion gate current at a low electrical field (> 0. 1 A/cm(2) at 1 V) caused by the scaling down of oxide thickness. The gate current in accumulation mode is smaller than that in inversion mode by more than two orders of magnitude at a low applied voltage (1 V). The bi-mode model proposed in this paper applies a voltage stress in the inversion mode and detects failure in the accumulation mode to enhance the robustness of the breakdown test and reduce the possibility of pseudo breakdown failure. With the proposed method, a shorter test time with an increased test pattern area to improve the efficiency of the breakdown test of ultrathin oxide is achieved.
Novel chip standby current prediction model and ultrathin gate oxide scaling limit
(2002-01-01)
Su, HD
;
Chiou, BS
;
Lu, PC
;
Chang, MH
;
Lee, KH
In deep sub-micron technology, leakage current of the oxide layer has a severe impact on chip power consumption due to the scaling down of oxide thickness. The inverter circuit model proposed in this paper provides a simple and quick method of predicting chip standby current. This model takes into account both the conventional device-off current and the inversion gate current, as compared to the conventional approach in which the gate leakage current is small and neglected. The temperature dependence study shows that the logarithm of the device-off current is inversely proportional to temperature. From 25 C, the device-off current increases tenfold for a temperature increase of 50 C, while the inversion gate current is almost temperature independent. Hence, a more aggressive oxide scaling rule could be employed in high-performance products operated at higher temperatures under the same device-off current/inversion gate current ratio.
Wafer bonding by Ni-induced crystallization of amorphous silicon
(2003-09-01)
Chao, CP
;
Wu, YCS
;
Lee, TL
;
Wang, YH
;
材料科學與工程學系
Wafer bonding by Ni-induced crystallization of amorphous silicon was investigated. It was found that wafers can be bonded through the crystallization of amorphous silicon at temperatures below 550 degreesC. Moreover, when 250 V was applied across the stacked samples, the bonding temperatures could be decreased to as low as 350 degreesC.