Browsing by Author "Chao, Chie-Min"

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A 52mW 1200MIPS compact DSP for multi-core media SoC
(2006)
Ou, Shih-Hao
;
Lin, Tay-Jyi
;
Huang, Chao-Wei
;
Kuo, Yu-Ting
;
Chao, Chie-Min
This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive microarchitecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3X performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18 mu m 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power.