Browsing by Author "Chao, Li-Chang"

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Novel yield model for integrated circuits with clustered defects
(2008-05-04)
Tong, Lee-Ing
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Chao, Li-Chang
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工業工程與管理學系
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Department of Industrial Engineering and Management
As wafer sizes increase, the clustering phenomenon of defects increases. Clustered defects cause the conventional Poisson yield model underestimate actual wafer yield, as defects are no longer uniformly distributed over a wafer. Although some yield models, such as negative binomial or compound Poisson models, consider the effects of defect clustering on yield prediction, these models have some drawbacks. This study presents a novel yield model that employs General Regression Neural Network (GRNN) to predict wafer yield for integrated circuits (IC) with clustered defects. The proposed method utilizes five relevant variables as input for the GRNN yield model. A simulated case is applied to demonstrate the effectiveness of the proposed model. (c) 2007 Elsevier Ltd. All rights reserved.
Wafer defect pattern recognition by multi-class support vector machines by using a novel defect cluster index
(2009-08-01)
Chao, Li-Chang
;
Tong, Lee-Ing
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
Wafer yield is an important index of efficiency in integrated circuit (IC) production. The number and cluster intensity of wafer defects are two key determinants of wafer yield. As wafer sizes increase, the defect cluster phenomenon becomes more apparent. Cluster indices currently used to describe this phenomenon have major limitations. Causes of process variation can sometimes be identified by analyzing wafer defect patterns. However, human recognition of defect patterns can be time-consuming and inaccurate. This Study presents a novel recognition system using multi-class Support vector machines with a new defect Cluster index to efficiently and accurately recognize wafer defect patterns. A simulated case demonstrates the effectiveness of the proposed model. (C) 2009 Elsevier Ltd. All rights reserved.