Browsing by Author "Chao, T. -S."

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A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing
(2014)
Lee, Y. -J.
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Cho, T. -C.
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Kao, K. -H.
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Sung, P. -J.
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Hsueh, F. -K.
For the first time, a novel junctionless (JL) FinFET structure with a shell doping profile (SDP) formed by molecular monolayer doping (MLD) method and microwave annealing (MWA) at low temperature is proposed and studied. Thanks to the ultra thin SDP leading to an easily-depleted channel, the proposed JLFinFET can retain the ideal subthreshold swing (similar to 60 mV/dec) at a high doping level according to simulations. Poly Si based JLFinFETs processed with MLD and MWA exhibit superior subthreshold swing (S.S. similar to 67mV/dec) and excellent on-off ratio (>10(6)) for both n and p channel devices. Threshold voltage (V-TH) variation due to random dopant fluctuation (RDF) is reduced in MLD-JLFinFETs, which can be attributed to the molecule self-limiting property of MLD on the Si surface and quasi-diffusionless MWA at low temperature. Our results reveal the potential of the proposed SDP enabling a JLFET showing reduced variation and outstanding performance for low power applications.
First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications
(2019-01-01)
Chang, S. -W.
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Sung, P. -J.
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Chu, T-Y.
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Lu, D. D.
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Wang, C. -J.
For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.
Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O-3 Treatment
(2018-01-01)
Yeh, M. -S.
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Luo, G. -L.
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Hou, F. -J.
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Sung, P. -J.
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Wang, C. -J.
Improved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. In-situ digital O-3 treatment in ALD chamber was adopted on the surface of Ge fin sidewall in order to reduce the roughness and etching damages through the GeO desorption mechanism. The treatment effects were checked by AFM and C-V measurements. By combining this treatment with optimized microwave annealing, sub-threshold slope and the I-ON/I-OFF ratio were remarkably improved in both n-finFET and p-finFET, and Ge CMOS inverters with high voltage gain of 50.3 V/V at low V-D = 0.6 V was realized. Finally, simulations on an ideal Ge CMOS inverter were presented.
Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability
(2017-01-01)
Su, C. -J.
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Hong, T. -C.
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Tsou, Y. -C.
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Hou, F. -J.
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Sung, P. -J.
Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. I-ON/I-OFF ratios higher than 10(7) and 10(6) for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.
High Performance Complementary Ge Peaking FinFETs by Room Temperature Neutral Beam Oxidation for Sub-7 nm Technology Node Applications
(2016-01-01)
Lee, Y. -J.
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Hong, T. -C.
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Hsueh, F. -K.
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Sung, P. J.
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Chen, C. -Y.
Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) and anisotropic neutral beam oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched Ge surface. The fabricated Ge peaking FinFETs possess several unique features: (1) A peaking fin configuration with a 6-nm top-gate formed by an anisotropic NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces by NB processes. (3) ION and Gm improvement by NB processes as compared to that by conventional inductively coupled plasma etching (ICP). (4) Recorded high I-ON/I-OFF ratio and low subthreshold swing (S.S. similar to 70 mV/dec.) of Ge n-FinFETs. (5) Excellent immunity for short channel effect of Ge FinFETs.
High Performance Silicon N-channel Gate-All-Around Junctionless Field Effect Transistors by Strain Technology
(2016)
Sung, P. -J.
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Cho, T. -C.
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Chen, P. -C.
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Hou, F. -J.
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Lai, C. -H
In this paper, strain effects on silicon n-channel gate-allaround (GAA) jucntionless field effect transistor (JLFET) are studied. By using tensile strain SiN layer, drive currents of the JLFETs show enhancement of up to 42%. The high performance strained JLFETs exhibit superior gate control (I-on/I-off > 10(9)) and ideal S.S. (65 mV/dec.) as a channel width scales down to 20 nm. Drive currents and leakage currents are improved simultaneously after inducing strain technology.
Microwave Annealing
(2012)
Lee, Yao-Jen
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Cho, T. -C.
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Chuang, S. -S.
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Hsueh, F. -K.
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Lu, Y. -L.
Microwave annealing of dopants in Si has been reported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However the details of the kinetics and mechanisms for microwave annealing are far from well understood. Comparisons between MWA and RTA of dopants in implanted Si has been investigated to produce highly activated junctions. First, As, P-31, and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 degrees C.
Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications
(2018-01-01)
Sung, P. -J.
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Chang, C. -Y.
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Chen, L. -Y.
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Kao, K. -H.
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Su, C. -J.
For the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 degrees C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.