Browsing by Author "Chao, TS"

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2-bit poly-Si-TFT nonvolatile memory using hafnium oxide, hafnium silicate and zirconium silicate
(2005)
Lin, YH
;
Chien, CH
;
Chou, TH
;
Chao, TS
;
Chang, CY
In this paper, we, for the first time, have successfully fabricated SONOS-type poly-Si-TFT memories employing three kinds of high-k dielectrics, including HfO(2), Hf-silicate and Zr-silicate, as the trapping layer with low-thermal budget processing. It was demonstrated that the fabricated memories exhibit good performance in terms of relatively large memory window, high program/erase speed (1ms/10ms), long retention time (> 10(6)S for 20% charge loss) and negligible read/write disturbances. In particular, 2-bit operation has been successfully demonstrated.
A comprehensive study of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFET's
(1999-09-01)
Wang, TH
;
Chiang, LP
;
Zous, NK
;
Hsu, CF
;
Huang, LY
The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFET's are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V-gs such as drain-to-source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account, The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current,:and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 Angstrom) n-MOSFET's, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 Angstrom) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation.
A domain partition approach to parallel adaptive simulation of dynamic threshold voltage MOSFET
(2002-08-01)
Li, YM
;
Chao, TS
;
Sze, SM
;
電子工程學系及電子研究所
;
友訊交大聯合研發中心
In this paper, we present a dynamic domain partition simulation technique for parallel numerical solutions of semiconductor device equations. Based on the adaptive finite volume method, a posteriori error estimation, and monotone iterative algorithm, this dynamic load balancing approach has been successfully developed and implemented on a Linux cluster with message passing interface library. The developed simulator is then applied to calculate the physical characteristics of deep submicron dynamic threshold voltage MOSFET (DTMOS). We simulate DTMOS with two different parallel algorithms: (1) 2D dynamic load balancing for parallel domain decomposition; (2) parallel I-V point simulation. Benchmark results show that a well-designed load balancing simulation can reduce the execution time up to an order of magnitude. Compared with the measured data, the simulated results for a 0.08 mum DTMOS are demonstrated to show the accuracy and efficiency of the method. (C) 2002 Elsevier Science B.V All rights reserved.
A new parallel adaptive finite volume method for the numerical simulation of semiconductor devices
(2001-12-15)
Li, YM
;
Liu, JL
;
Chao, TS
;
Sze, SM
;
應用數學系
Based on adaptive finite volume approximation, a posteriori error estimation, and monotone iteration, a novel system is proposed for parallel simulations of semiconductor devices. The system has two distinct parallel algorithms to perform a complete set of I-V simulations for any specific device model. The first algorithm is a domain decomposition on I-irregular unstructured meshes whereas the second is a parallelization of multiple I-V points. Implemented on a Linux cluster using message passing interface libraries, both algorithms are shown to have excellent balances on dynamic loading and hence result in efficient speedup. Compared with measurement data, computational results of sub-micron MOSFET devices are given to demonstrate the accuracy and efficiency of the system. (C) 2001 Elsevier Science B.V. All rights reserved.
A novel planarization of oxide-filled shallow-trench isolation
(1997-01-01)
Cheng, JY
;
Lei, TF
;
Chao, TS
;
Yen, DLW
;
Lin, CJ
Two planarization approaches of the oxide-filled trench isolation have been evaluated. Results show that the oxide-filled shallow-trench isolation technology based on a chemical-mechanical polishing (CMP) process is difficult to control and has a poor uniformity. It also results in a dishing effect in wide field regions. On the other hand, a new planarization process can achieve an excellent uniformity and fully planar surface by using a combination of a masking polysilicon layer based on a CMP process, selective wet etching for oxide refill on active regions, short-time CMP process for oxide refill, and reactive ion etching etchback. Results also show that the high breakdown yield of the gate oxide and the low leakage current of the n(+)/p junction diodes with the novel planarization process demonstrates extremely low defect density from this process. This new process is a very promising candidate for oxide-filled shallow-trench isolation.
A novel shallow trench isolation technique
(1997-03-01)
Cheng, JY
;
Lei, TF
;
Chao, TS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Shallow-trench isolation processes which involve refilling using deposition of oxide and polysilicon were investigated. Our results show that the oxide-filled shallow-trench isolation technology based on chemical-mechanical polishing (CMP) is difficult to control and results in poor uniformity. Use of this technology also involves in the dishing effect in wide field regions. However, shallow-trench isolation technology using a masking nitride layer, polysilicon refill, the CMP process with high etch selectivity, and local oxidation of polysilicon is easily implemented and absolutely field oxide encroachment (bird's beak) free. Although the CMP process results in the dishing effect in wide field regions, the local oxidation of polysilicon can reduce the amount of dishing. The polysilicon-filled shallow-trench isolation process can also achieve excellent uniformity across 6-inch diameter silicon wafers due to the high etching selectivity of polysilicon to chemical-vapor-deposited (CVD) oxide and SiN. Moreover, the n(+)/p junction leakage current of polysilicon-filled shallow trenches is comparable to that of oxide-filled shallow trenches. This simple and easily controllable process is a very promising candidate for shallow trench isolation.
A novel Si-B diffusion source for p(+)-poly-Si gate
(1999-10-01)
Chao, TS
;
Kuo, CP
;
Chen, TP
;
Lei, TF
;
電子工程學系及電子研究所
In this paper, we report a novel Si-B diffusion source for p(+)-polySi gate p-metal oxide-semiconductor field effect transistors (pMOSFETs). It is found that boron penetration can br effectively suppressed using this process. All the electrical properties of the MOS capacitors are significantly improved over the conventional BF2+ or B+-implanted samples. This process is very promising for fabrication of future surface-channel p-MOSFETs. (C) 1999 The Electrochemical Society. S0013-4651(99)03-017-7. All rights reserved.
A one-step single-cleaning solution for CMOS processes
(2003-09-01)
Chao, TS
;
Yeh, CH
;
Pan, TM
;
Lei, TF
;
Li, YH
In this paper, we demonstrate a one-step single-cleaning solution to replace the conventional RCA two-step cleaning method for complementary metal oxide semiconductor (CMOS) processes. We found the performance of devices fabricated using this new recipe is comparable or even better than that of devices fabricated using the conventional RCA method. The benefits of this method are more efficient removal of contaminants, improved driving current of devices, simpler processing, fewer steps in cleaning, time savings, reduction of cost and of chemical waste, and reduced impact on the environment. (C) 2003 The Electrochemical Society.
A practical implementation of parallel dynamic load balancing for adaptive computing in VLSI device simulation
(2002)
Li, Y
;
Sze, SM
;
Chao, TS
;
電子工程學系及電子研究所
;
友訊交大聯合研發中心
We present a new parallel semiconductor device simulation using the dynamic load balancing approach. This semiconductor device simulation based on the adaptive finite volume method with a posteriori error estimation has been developed and successfully implemented on a 16-PC Linux cluster with a message passing interface library. A constructive monotone iterative technique is also applied for solution of the system of nonlinear algebraic equations. Two different parallel versions of the algorithm to perform a complete device simulation are proposed. The first is a dynamic parallel domain decomposition approach, and the second is a parallel current-voltage characteristic points simulation. This implementation shows that a well-designed load balancing simulation can significantly reduce the execution time up to an order of magnitude. Compared with the measured data, numerical results on various submicron VLSI devices are presented, to show the accuracy and efficiency of the method.
A study on the radiation hardness of flash cell with horn-shaped floating-gate
(1997-09-01)
Huang, TY
;
Jong, FC
;
Chao, TS
;
Lin, HC
;
Leu, LY
The effects of radiation on the characteristics of split-gate electrical erasable programmable read only memory (EEPROM)/flash cells with recently-proposed horn-shaped floating gates are studied in terms of cell read current; data retention, cycling endurance, program/erase efficiency, threshold voltage and junction leakage. Our results show that the cells appear to survive after 1 Mrad (Si) Co-60 irradiation. Moreover, the after-irradiation cell read current actually increases in the ''erase'' (i.e., low-threshold voltage, high-conducting) state (i.e., improves), albeit the cell read current also increases in the ''program'' (i.e., high-threshold voltage, low-conducting) state (i.e., a degradation). Our results also show that, despite an improvement in the initial read current in the ''erase'' state immediately after radiation, the write/erase cycling endurance of the flash cells is significantly impeded after irradiation, due to a much faster ''window closure'' rate in the ''erase'' state, although the cell read current is found to remain relatively stable in the ''program'' state after cycling.
A study on the radiation hardness of flash cell with horn-shaped floating-gate
(1997-09-01)
Huang, TY
;
Jong, FC
;
Chao, TS
;
Lin, HC
;
Leu, LY
The effects of radiation on the characteristics of split-gate electrical erasable programmable read only memory (EEPROM)/flash cells with recently-proposed horn-shaped floating gates are studied in terms of cell read current; data retention, cycling endurance, program/erase efficiency, threshold voltage and junction leakage. Our results show that the cells appear to survive after 1 Mrad (Si) Co-60 irradiation. Moreover, the after-irradiation cell read current actually increases in the ''erase'' (i.e., low-threshold voltage, high-conducting) state (i.e., improves), albeit the cell read current also increases in the ''program'' (i.e., high-threshold voltage, low-conducting) state (i.e., a degradation). Our results also show that, despite an improvement in the initial read current in the ''erase'' state immediately after radiation, the write/erase cycling endurance of the flash cells is significantly impeded after irradiation, due to a much faster ''window closure'' rate in the ''erase'' state, although the cell read current is found to remain relatively stable in the ''program'' state after cycling.
An accurate hot carrier reliability monitor for deep-submicron shallow S/D junction thin gate oxide n-MOSFET's
(1999)
Chung, SS
;
Chen, SJ
;
Yih, CM
;
Yang, WJ
;
Chao, TS
In this paper, an accurate criterion has been proposed for reliability evaluation of state-of-the-art deep-submicron S/D extension n-MOSFET's. A new monitor for HC reliability evaluation has been developed using total values of N-it in the effective channel length region, instead of commonly used substrate current(I-B), impact ionization rate (I-D/I-B), or peak/average N-it values. An accurate degradation model has thus been developed based on the N-it distribution and mobility scattering effect. Moreover, this approach has been successfully used to demonstrate the feasibility for gate-engineering studies.
An anomalous crossover in Vth roll-off for indium-doped nMOSFETs
(2000-09-01)
Chang, SJ
;
Chang, CY
;
Chen, CM
;
Chou, JW
;
Chao, TS
The effects of indium channel implant energy on short-channel effect (SCE) and narrow channel effect (NCE) were studied on NMOS devices down to 0.1 mu m channel length. An anomalous crossover in Vth roll-off curves was observed, for the first time, on indium-implanted splits with different implant energies. This intriguing finding, together with the observed reduction in reverse narrow channel effect (RNCE) and effective channel length with reducing indium implant energy, can be consistently explained by the suppression of transient enhanced diffusion (TED) of channel impurity due to indium deactivation.
Characteristics of polysilicon oxides combining N2O nitridation and CMP processes
(2000-08-01)
Lei, TF
;
Chen, JH
;
Wang, MF
;
Chao, TS
;
電子工程學系及電子研究所
This paper present a high-quality polysilicon oxide combining N2O nitridation and chemical mechanical polishing (CMP) processes. Experimental results indicate that polyoxide grown on the CMP sample exhibits a lower leakage current, higher dielectric breakdown field, higher electron barrier height, less electron trapping rate, higher charge-to-breakdown (Q(bd)), and lower density of trapping charge than those of non-CMP samples. In addition, the CMP process enhances nitrogen incorporation at the interface by the N2O nitridation, ultimately improving the polyoxide quality, Moreover, the CMP process smooths the surface of polysilicon and this planar surface reduces the out-diffusion of the phosphorous during thermal oxidation.
Characteristics of TEOS polysilicon oxides: Improvement by CMP and high temperature RTA N-2/N2O annealing
(2000-11-01)
Chen, JH
;
Lei, TF
;
Chen, JH
;
Chao, TS
;
電子工程學系及電子研究所
The integrity of tetraethylorthosilicate (TEOS) polyoxide using chemical mechanical polishing (CMP) plus a high temperature rapid thermal annealing (RTA) step was studied in this work. The surface morphology of polysilicon is improved after a CMP process. Polyoxides deposited by low pressure chemical vapor deposition (LPCVD) TEOS in conjunction with CMP and RTA N-2/N2O annealing exhibit a better current-electric field (J-E) curve, higher charge to breakdown ratio, and lower electron trapping rate. In addition, the composite bilayer (TEOS deposited and thermally grown by RTA) polyoxide film introduces an asymmetry of electrical leakage current, trapping characterization, and charge to breakdown, with respect to the injection of different polarity (+V-g and -V-g) (C) 2000 The Electrochemical Society. S0013-4651(00)01-051-X. All rights reserved.
Characterization of interfacial layer of ultrathin Zr silicate on Si(100) using spectroscopic ellipsometry and HRTEM
(2004-05-01)
Ahn, H
;
Chen, HW
;
Landheer, D
;
Wu, X
;
Chou, LJ
Optical properties and the film thickness of interfacial layer formed between the ultrathin as-deposited Zr silicate films and the Si substrate were investigated by the variable-angle spectroscopic ellipsometry (SE), the high-resolution transmission electron microscopy (HRTEM), and X-ray photoelectron spectroscopy (XPS). Five Zr silicate films were deposited by using oxygen-based Zr(O-i-Pr)(2)(thd)(2) and Si(O-t-Bu)(2)(thd)(2) as precursors in a pulse-mode metalorganic chemical-vapor deposition (MOCVD) apparatus to investigate the influence of the choice of ambient gas (oxygen or NO) on the formation of the interfacial layers during the oxidation and the deposition of the Zr silicate films. HRTEM images clearly show the existence of the amorphous interfacial layer below the Zr silicate layer. The interfacial layers are found to be Zr-free from the XPS study. In SE analysis, the interfacial layers were described best as the mixture of SiO2 and SiO in the Bruggeman effective medium approximation (BEMA). The evident reduction of the interfacial layer due to the intentionally grown ultrathin oxynitride buffer layer was observed for the Zr silicate film deposited under a carefully designed growing condition. Any source of oxygen during the growth of the film results in the thicker, but self-limited interfacial layer. (C) 2004 Elsevier B.V. All rights reserved.
Characterization of polysilicon oxides thermally grown and deposited on the polished polysilicon films
(1998-04-01)
Lei, TF
;
Cheng, JY
;
Shiau, SY
;
Chao, TS
;
Lai, CS
This work examines the characteristics of polyoxides thermally grown and deposited an polished polysilicon films. A well-controlled chemical mechanical polishing (CMP) process is also presented to achieve a planar surface morphology Tot polysilicon films. The thermally-grown and deposited polyoxides on the polished polysilicon films exhibit a lower leakage current, higher dielectric breakdown field, higher electron barrier height, lower electron trapping, rate, lower density of trapped charges, and markedly higher charge to breakdown (Q(bd)) than the conventional polyoxide. In particular, the deposited polyoxide on the polished polysilicon film has the highest dielectric breakdown field, lowest electron trapping rate, and highest charge to breakdown due to the planar polyoxide/polysilicon interface. In addition, experimental results indicate that the trapped charges of the polished samples are located in the polyoxides' upper portion, which differs from conventional polyoxides. Undoubtedly, the deposited polyoxide on the polished polysilicon film considered herein is the most promising candidate to yield optimum characteristics of polyoxide.
Characterization of thin ZrO2 films deposited using Zr(O '-Pr)(2)(thd)(2) and O-2 on Si(100)
(2002-05-01)
Chen, HW
;
Landheer, D
;
Wu, X
;
Moisa, S
;
Sproule, GI
The properties of ZrO2 films deposited using molecular oxygen and a recently developed precursor, zirconium Zr(O-i-Pr)(2)(thd)(2) have been investigated. The organometallic was dissolved as a 0.15 molar solution in octane and introduced into the deposition chamber using a liquid injection system. The deposition rate was insensitive to molecular oxygen flow but changed with liquid injection rate and was thermally activated in the range 390 degreesC-550 degreesC. Carbon concentrations, <0.1 at.%, the detection limit of the x-ray photoelectron spectroscopy depth profiling measurements, were obtained at the lowest deposition temperatures and deposition rates. High-resolution transmission electron microscopy showed the films to be polycrystalline as deposited, with a zirconium silicate interfacial layer. After proper annealing treatments, an equivalent oxide thickness (EOT) of around 2.3 urn has been achieved for a 5.2 nm thick film, with a leakage current two orders of magnitude lower than that Of SiO2 with the same EOT. Promising capacitance-voltage characteristics were also achieved, but some improvements are required if these films are to be used as a gate insulator. (C) 2002 American Vacuum Society.
Characterization of ultrathin oxynitride (18-21 angstrom) gate dielectrics by NH3 nitridation and N2O RTA treatment
(2001-05-01)
Pan, TM
;
Lei, TF
;
Wen, HC
;
Chao, TS
;
電子工程學系及電子研究所
In this paper, we developed a new method to grow robust ultrathin oxynitride (E-OT = 18 Angstrom) film with effective dielectric constant of 7.15. By NH3-nitridation of Si substrate, grown ultrathin Si3N4 with N2O annealing shows excellent electrical properties in terms of significant lower leakage current, very low bulk trap density and trap generation rate, and high endurance in stressing, In addition, this oxynitride film exhibits relatively weak temperature dependence due to a Fowler-Nordheim (FN) tunneling mechanism. This dielectric film appears to be promising for future ultralarge scale integrated (ULSI) devices.
Comparison of novel cleaning solutions, with various chelating agents for post-CMP cleaning on poly-Si film
(2001-11-01)
Pan, TM
;
Lei, TF
;
Ko, FH
;
Chao, TS
;
Chiu, TH
In this study, various cleaning solutions containing chelating agents with carboxyl acid group (-COOH), such as ethylenediaminetetraacetic acid, citric acid and oxalic acid, were developed for post-poly-Si CMP cleaning. The chelating agent and tetramethylammonium hydroxide (TMAH) were simultaneously added into 2% ammonium hydroxide alkaline solution to promote the removal efficiency on particles and metallic impurities. The effectiveness of various cleaning recipes and their interaction mechanism with poly-Si surface were studied. We could explain the surface behavior of various cleaning solutions by the different molecular size and charge of chelating agents. Based on the mechanism, the behavior of surface particle and metallic impurity can be realized. The co-existence of TMAH with citric acid or oxalic acid in the alkaline cleaning solutions can significantly enhance the electrical property for the capacitor.