Browsing by Author "Chao, Yu-Te"

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A statistical model for simulating the effect of UPS TFT device variation for SOP applications
(2007-12-01)
Tai, Ya-Hsiang
;
Huang, Shih-Che
;
Chen, Wan-Ping
;
Chao, Yu-Te
;
Chou, Yen-Pang
In this paper, the variation characteristics of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) are investigated with a statistical approach. A special layout is proposed to investigate the device variation with respect to various devices distances. Two non-Gaussian equations are proposed to fit the device parameter distributions, whose the coefficients of determination (R(2)) are both near 0.9, reflecting the validity of the model. Two benchmark circuits are used to compare the difference between the proposed model and the conventional Gaussian distribution for the device parameter distribution. The output behaviors of the digital and analog circuits show that the variation in the short range would greatly affect the performance of the analog circuits and would instead be averaged in the digital circuits.
Capacitance-voltage behaviors of the LTPS TFTs before and after DC stress explained by the slicing model
(2007)
Kuo, Yan-Fu
;
Huang, Shih-Che
;
Chao, Yu-Te
;
Tai, Ya-Hsiang
;
光電工程學系
The proposed analytical circuit based on the slicing model further explains the behavior of the gate-to-source capacitance CGS and gate-to-drain capacitance CGD curves of the LTPS TFT at different measuring frequencies. The degradation mechanisms and damaged locations can be identified according to the frequency responses of the CGS and CGD curves.